本文選題：量子元胞自動機 + 容錯性　； 參考：《合肥工業(yè)大學》2017年碩士論文

【摘要】：以CMOS器件為核心的集成電路技術一直以來遵循著摩爾定律飛速發(fā)展,隨著芯片制造工藝的進步,器件的尺寸越來越小。器件尺寸的減小使得其物理基礎發(fā)生根本變化,導致電路功能出現(xiàn)錯誤,出現(xiàn)了高功耗、高密度、復雜布線與串擾等問題,嚴重影響了集成電路的發(fā)展。因此廣大科研工作者尋找代替?zhèn)鹘y(tǒng)CMOS器件的新型器件。其中,出現(xiàn)于20世紀90年代的量子元胞自動機(Quantum-dot CellularAutomata,QCA)是眾多替代器件中的一種代表性器件。QCA提供了一種全新的編碼、傳遞、轉換二進制信息的方式。QCA電路已被廣泛研究,傳統(tǒng)電路中的諸如存儲器、觸發(fā)器、加法器、乘法器等已經(jīng)可以實現(xiàn),而且由QCA搭建的FPGA系統(tǒng)也有所發(fā)展。除此之外,QCA電路的穩(wěn)定性以及容錯特性也有科研人員在研究。QCA電路的具體物理實現(xiàn)依靠于電路良好的可靠性和容錯性。本文致力于QCA電路的可靠性分析和容錯性設計。在設計組合邏輯電路方面,利用提出的3×5模塊,來優(yōu)化QCA基本邏輯單元,使得它們不僅保持正確的邏輯功能,而且在缺失一個或者兩個元胞的情況下能夠具有良好的容錯性。利用提出的基本單元來實現(xiàn)了加法器電路,將其與其他存在的電路進行容錯性比較發(fā)現(xiàn),提出的結構優(yōu)化了電路的容錯性。隨后在時序邏輯電路方面,提出了一種改進的雙邊沿觸發(fā)結構及其相應的JK觸發(fā)器電路與D觸發(fā)器,通過概率轉移矩陣(Probabilistic Transfer Matrix,PTM)和缺陷研究來分析該觸發(fā)結構,結果表明改進的觸發(fā)結構可靠性更高,并利用模塊垂直堆疊方法來優(yōu)化JK觸發(fā)器電路,與之前的設計相比,新結構電路的元胞數(shù)和整體面積均有所減少。經(jīng)QCADesigner仿真驗證,所有電路均實現(xiàn)正確的邏輯功能。
[Abstract]:The integrated circuit technology with CMOS devices as the core has been following the rapid development of Moore's law. With the development of chip manufacturing technology, the device size is becoming smaller and smaller. The reduction of device size causes fundamental changes in the physical basis of the device, resulting in errors in circuit functions, high power consumption, high density, complex wiring and crosstalk problems, which seriously affect the development of integrated circuits. Therefore, researchers are looking for new devices instead of traditional CMOS devices. Quantum-dot cellular automata (QCA), which appeared in the 1990s, is a representative device of many alternative devices. QCA provides a new way of encoding, transferring and converting binary information. The QCA circuit has been widely studied. Traditional circuits such as memory, flip-flop, adder, multiplier and so on have been implemented, and the FPGA system built by QCA has also been developed. In addition, the stability and fault-tolerant characteristics of QCA circuits are also studied by researchers. The physical realization of QCA circuits depends on the good reliability and fault-tolerance of the circuits. This paper is devoted to the reliability analysis and fault-tolerant design of QCA circuits. In the design of combinatorial logic circuits, the proposed 3 脳 5 modules are used to optimize QCA basic logic units so that they can not only maintain correct logic functions, but also have good fault tolerance in the absence of one or two cells. The proposed basic unit is used to realize the adder circuit. Compared with other existing circuits, it is found that the proposed structure optimizes the fault tolerance of the circuit. In the aspect of sequential logic circuit, an improved two-sided trigger structure and its corresponding JK flip-flop circuit and D-flip-flop are proposed. The trigger structure is analyzed by probabilistic transfer matrix (probabilistic transfer matrix) and defect analysis. The results show that the improved trigger structure is more reliable, and the JK flip-flop circuit is optimized by module vertical stacking method. Compared with the previous design, the cell number and the overall area of the new structure circuit are reduced. The results of QCA designer simulation show that all circuits have correct logic function.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TP332.2

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本文編號：2026400