本文選題：寄存器文件 + 全定制設(shè)計(jì)��； 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：YHFT-DX是采用65納米工藝自主研發(fā)的高頻、高性能32位定點(diǎn)超長(zhǎng)指令字?jǐn)?shù)字信號(hào)處理器，其中寄存器文件是該處理器的性能瓶頸和設(shè)計(jì)難點(diǎn)之一。本文根據(jù)YHFT-DX的總體結(jié)構(gòu)和性能要求，確定了對(duì)該多端口寄存器文件進(jìn)行全定制設(shè)計(jì)的技術(shù)路線，設(shè)計(jì)實(shí)現(xiàn)了一款13讀9寫、支持64位長(zhǎng)型數(shù)據(jù)的32×32位寄存器文件，并對(duì)寄存器文件進(jìn)行了可測(cè)性設(shè)計(jì)和低功耗設(shè)計(jì)。所設(shè)計(jì)的寄存器文件版圖面積為266×302μm2，在YHFT-DX數(shù)字信號(hào)處理器芯片中得到了應(yīng)用，流片后的芯片測(cè)試結(jié)果表明：典型條件下隨機(jī)讀寫的平均功耗為8mW，，最差條件下工作頻率可以達(dá)到800MHz，達(dá)到了設(shè)計(jì)目標(biāo)。 本文的主要貢獻(xiàn)和創(chuàng)新點(diǎn)集中體現(xiàn)在以下幾個(gè)方面： 1.對(duì)YHFT-DX寄存器文件進(jìn)行了功能設(shè)計(jì)、時(shí)序設(shè)計(jì)以及結(jié)構(gòu)設(shè)計(jì)，確定了定向通路機(jī)制，避免了寫后讀數(shù)據(jù)相關(guān)。根據(jù)長(zhǎng)型數(shù)據(jù)訪問特點(diǎn)，采用端口復(fù)用、分體布局技術(shù)在寄存器內(nèi)部把端口數(shù)目從13讀9寫減少為10讀6寫，將存儲(chǔ)陣列中端口數(shù)目和譯碼器數(shù)目減少了6個(gè)，使版圖面積減少了22%。 2.采用全掃描設(shè)計(jì)方法來(lái)增加寄存器文件的可測(cè)試性，從而實(shí)現(xiàn)寄存器文件可觀察性、可控制性等可測(cè)試性設(shè)計(jì)目標(biāo)，并從以下方面體現(xiàn)其可測(cè)性：從任一寫端口向任一寄存器寫入數(shù)據(jù)可觀察；從任一讀端口向任一寄存器文件讀數(shù)據(jù)，或者任一讀端口通過定向通路向任一寫端口讀數(shù)據(jù)可觀察；輸入端口的控制信號(hào)實(shí)現(xiàn)對(duì)寫地址、寫使能、寫數(shù)據(jù)和讀數(shù)據(jù)的輸入和輸出工作狀態(tài)可控制。 3.采用邏輯優(yōu)化、操作數(shù)隔離、門控時(shí)鐘、混合閾值、多級(jí)譯碼、電路轉(zhuǎn)換等多種低功耗設(shè)計(jì)技術(shù)，降低了動(dòng)態(tài)功耗和漏流功耗。典型條件下隨機(jī)讀寫平均功耗為8mW。 4.采用結(jié)構(gòu)化版圖設(shè)計(jì)減少了版圖面積。同時(shí)加入可測(cè)試設(shè)計(jì)后，通過改變電路結(jié)構(gòu)并運(yùn)用結(jié)構(gòu)化版圖設(shè)計(jì)方法，使得寄存器文件版圖面積比傳統(tǒng)版圖設(shè)計(jì)方法減少了15%。通過更優(yōu)的電路結(jié)構(gòu)，提高了寄存器的性能，在譯碼、存儲(chǔ)和定向通路中使用了低閾值技術(shù)降低了延時(shí)，頻率在最差條件下可以達(dá)到800MHz。
[Abstract]:YHFT-DX is a high frequency, high performance 32 bit fixed point ultra long instruction word digital signal processor developed by 65 nm process. Register file is one of the performance bottlenecks and design difficulties of the processor. According to the overall structure and performance requirements of YHFT-DX, the technical route of fully customizing the multi-port register file is determined in this paper. A 32 脳 32 bit register file with 13 read and 9 writes and supporting 64 bit long data is designed and implemented. The register file is designed for testability and low power consumption. The designed register file has a layout area of 266 脳 302 渭 m ~ 2, which has been applied in YHFT-DX digital signal processor chip. The chip test results after streaming show that the average power consumption of random reading and writing is 8 MW under typical conditions, and the working frequency can reach 800 MHz under the worst condition, which achieves the design goal. The main contributions and innovations of this paper are embodied in the following aspects: 1. The function design, timing design and structure design of the YHFT-DX register file are carried out, and the directional path mechanism is determined to avoid the post-write data correlation. According to the characteristics of long data access, port multiplexing is adopted. The split layout technique reduces the number of ports from 13 read 9 write to 10 read 6 write in the register, and reduces the number of ports and decoders in the memory array by 6. Reduce the layout area by 22.2. The full scan design method is used to increase the testability of register files, so as to realize the testability design goals of register files, such as observability, controllability, etc. The testability can be observed by writing data from any write port to any register, reading data from any read port to any register file, or reading data from any read port to any write port through a directional path. Input port control signal to write address, write enable, write data and read data input and output working state can be controlled. 3. Low power design techniques such as logic optimization, Operand isolation, gated clock, hybrid threshold, multistage decoding and circuit conversion are used to reduce dynamic power consumption and leakage power consumption. Under typical conditions, the average power consumption of random reading and writing is 8 MW. 4. Structural layout design reduces layout area. After adding testability design, by changing the circuit structure and using the structural layout design method, the register file layout area is reduced by 15% compared with the traditional layout design method. The performance of the register is improved by better circuit structure, and the delay is reduced by using low threshold technique in decoding, storage and orientation paths, and the frequency can reach 800MHz under the worst conditions.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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本文編號(hào)：2021315