本文選題：非揮發(fā)性存儲器件 + 硅納米晶體��； 參考：《電子科技大學》2012年碩士論文

【摘要】：在應對半導體制造技術不斷發(fā)展的潮流時，傳統(tǒng)非揮發(fā)性存儲器件的連續(xù)浮柵結(jié)構制約了其向更小尺寸發(fā)展，需要在保持浮柵存儲器件工作機理不變的前提下，繼續(xù)發(fā)展浮柵存儲器。納米晶體浮柵存儲器件是解決傳統(tǒng)浮柵存儲器件面臨的小尺寸限制的有效辦法，這為納米晶體浮柵存儲器件的發(fā)展提供了極大的動力。 本文闡述了納米晶體浮柵存儲器件的發(fā)展背景，包括非揮發(fā)性存儲器的市場前景和發(fā)展形勢，以及納米晶體浮柵存儲器件的優(yōu)勢等；介紹了非揮發(fā)性存儲器件的理論知識和納米晶體浮柵存儲器件的納米特性；并利用工藝仿真軟件Tsuprem4和器件仿真軟件Medici對硅納米晶體浮柵存儲器件建模和仿真了其電學特性等；試制了不同溝道長度的N溝道硅納米晶體浮柵存儲器件并對其做了常規(guī)的測試分析。 本文具體完成以下工作： （a）、利用Tsuprem4建立了硅納米晶體浮柵存儲器件的仿真模型，然后利用Medici對模型的電學特性進行仿真分析，另外研究了硅納米晶體浮柵存儲器件的幾個重要結(jié)構參數(shù)對存儲器件的存儲特性（主要是存儲窗口）的影響，對硅納米晶體浮柵存儲器件的數(shù)據(jù)保持能力進行了Matlab建模分析。 （b）、討論了硅納米晶體的制備方法和利用標準2μm CMOS工藝制備硅納米晶體浮柵存儲器件的工藝流程，并將離子注入和退火制備硅納米晶體的方法加入NTU-MFL2μm NWell CMOS中的Single-Poly-Single-Metal (SPSM)標準CMOS工藝中，成功試制了一批具有不同溝道長度的N溝道硅納米晶體浮柵存儲器件。 （c）、利用搭建的測試平臺對制備出來的硅納米晶體浮柵存儲器件進行了室溫下的測試分析，包括TEM切片分析、寫入/擦除操作脈沖與存儲窗口的關系，，并測試分析了存儲器件的耐擦寫能力和數(shù)據(jù)保持能力。測試結(jié)果表明，試制的硅納米晶體浮柵存儲器件具有較大的存儲窗口，優(yōu)良的耐擦寫能力和數(shù)據(jù)保持能力。
[Abstract]:In response to the continuous development of semiconductor manufacturing technology, the continuous floating gate structure of traditional non-volatile memory devices restricts its development to smaller dimensions, so it is necessary to keep the working mechanism of floating gate memory devices unchanged. Continue to develop floating gate memory. Nanocrystalline floating gate memory device is an effective method to solve the small size limitation of traditional floating gate memory device. This provides a great impetus for the development of nanocrystalline floating gate memory devices. This paper describes the development background of nanocrystalline floating gate memory devices, including the market prospect and development situation of non-volatile memory. And the advantages of nanocrystalline floating gate memory devices, the theoretical knowledge of non-volatile memory devices and the nanometer characteristics of nanocrystalline floating gate memory devices are introduced. The process simulation software Tsuprem4 and the device simulation software Medici are used to model and simulate the electrical properties of silicon nanocrystalline floating gate memory device. N-channel silicon nanocrystalline floating gate memory devices with different channel lengths have been fabricated and analyzed. In this paper, the following work has been done: (1) the simulation model of silicon nanocrystalline floating gate memory device is established by Tsuprem4. Then the electrical characteristics of the model are simulated and analyzed by Medici, and the influence of several important structure parameters of silicon nanocrystalline floating gate memory device on the memory characteristics (mainly memory window) is studied. The data retention ability of silicon nanocrystalline floating gate memory device is modeled and analyzed by Matlab. The fabrication method of silicon nanocrystalline and the process of fabricating silicon nanocrystalline floating gate memory device using standard 2 渭 m CMOS process are discussed. The method of ion implantation and annealing to fabricate silicon nanocrystalline is added to the standard CMOS process of Single-Poly-Single-Metal SPSMin NTU-MFL2 渭 m well CMOS. A batch of N-channel silicon nanocrystalline floating gate memory devices with different channel lengths have been successfully manufactured. The fabricated silicon nanocrystalline floating gate memory devices have been tested and analyzed at room temperature, including TEM slice analysis. The relationship between the write / erase operation pulse and the memory window is also tested and analyzed, and the erasability and data retention of the memory device are tested and analyzed. The test results show that the fabricated silicon nanocrystalline floating gate memory device has a large memory window, excellent erasability and data retention.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333

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本文編號：2009392