本文選題：nvSRAM + 低功耗��； 參考：《安徽大學(xué)》2017年碩士論文

【摘要】：隨著半導(dǎo)體產(chǎn)業(yè)不斷壯大,制造工藝飛速提升使得MOS管尺寸不斷縮小,但不斷縮小的尺寸導(dǎo)致SRAM對電路制造工藝的偏差要求更加的苛刻,對于工藝波動更加敏感,性能也越發(fā)不穩(wěn)定。然而市場對于高速高性能低功耗的SRAM需求日益增加。為了滿足低功耗的市場需求,降低電源電壓技術(shù)已經(jīng)被提出,然而降低電壓將導(dǎo)致其靜態(tài)噪聲容限減小從而導(dǎo)致SRAM的穩(wěn)定性進(jìn)一步降低。并且隨著SRAM單元數(shù)目的不斷增加,SRAM在靜態(tài)保持狀態(tài)下的泄漏功耗仍然不容忽視。尤其是對于一些常關(guān)斷的系統(tǒng)而言泄漏功耗遠(yuǎn)大于動態(tài)功耗時(shí),減小泄漏功耗對于增加電池壽命至關(guān)重要。此外,對于傳統(tǒng)SRAM在系統(tǒng)電源關(guān)斷后,存儲數(shù)據(jù)會隨之消失,當(dāng)再次上電時(shí)SRAM單元存儲的信息為隨機(jī)值,無法恢復(fù)掉電前存儲的數(shù)據(jù),這對于需要保存大量現(xiàn)場數(shù)據(jù)及各種系統(tǒng)參數(shù)的應(yīng)用系統(tǒng)來說無疑是不允許的。雖然非揮發(fā)性存儲器有掉電后保存數(shù)據(jù)的能力,但其速度慢無法替代SRAM高速高性能低功耗的優(yōu)勢。為了保留SRAM在芯片上的優(yōu)勢,許多芯片采用"雙宏結(jié)構(gòu)"(two-macro),該結(jié)構(gòu)包含易失性與非易失性存儲器,正常工作時(shí)與SRAM工作原理相同,在掉電時(shí)用非易失性存儲器備份SRAM數(shù)據(jù),再次上電時(shí)由非易失性存儲器將SRAM掉電前的數(shù)據(jù)寫回SRAM,在實(shí)現(xiàn)SRAM掉電信息存儲同時(shí)保留SRAM高速高性能低功耗優(yōu)勢,然而這種方法采用逐字傳遞易失(volatile)與非易失性存儲器(nonvolatile memories)之間的數(shù)據(jù),掉電備份與上電恢復(fù)數(shù)據(jù)速度慢,過長的掉電與上電時(shí)間不但降低了速度同時(shí)可能引起數(shù)據(jù)出錯。為了降低SRAM靜態(tài)保持功耗完成SRAM掉電數(shù)據(jù)存儲,本文基于阻變隨機(jī)存取存儲器(RRAM)提出幾種非易失性靜態(tài)隨機(jī)存儲器(nonvolatile SRAM)。通過仿真對比分析了幾種方案的優(yōu)缺點(diǎn),首先是調(diào)節(jié)驅(qū)動管尺寸實(shí)現(xiàn)可預(yù)知SRAM上電狀態(tài),該方案由于增加了每個(gè)單元尺寸相對于傳統(tǒng)8T2R結(jié)構(gòu)面積減小不明顯,且恢復(fù)率較低,隨后又提出打斷SRAM放電路徑實(shí)現(xiàn)可預(yù)知恢復(fù)方案,該方案節(jié)省了大量芯片面積,寫能力顯著提高,但同樣恢復(fù)率較低,為此最終提出了各方面性能顯著提升的方案。該電阻非易失性存儲單元由7個(gè)晶體管和一個(gè)阻變隨機(jī)存取存儲器構(gòu)成,包含一個(gè)非易失存儲器(1T1R)和一個(gè)標(biāo)準(zhǔn)6管SRAM單元,而在nvSRAM每一列外加一個(gè)NMOS管構(gòu)成本文提出的非易失平均7T1RnvSRAM(NVA-7T1R)。與現(xiàn)有幾種nvSRAM對比本文提出的方案具有面積小,速度快,功耗低,讀寫能力強(qiáng)等優(yōu)勢。每列增加的下拉尾管極大的提升了單元寫能力,與傳統(tǒng)SRAM相比寫能力提升近1倍。在數(shù)據(jù)恢復(fù)階段由于打破了 SRAM耦合反相器的鎖存,上電恢復(fù)SRAM數(shù)據(jù)時(shí)恢復(fù)速度為以往7T1R結(jié)構(gòu)的2.5倍,單元直流功耗減小了 63%。
[Abstract]:With the continuous expansion of semiconductor industry, the rapid improvement of manufacturing process makes the size of MOS tube shrink, but the shrinking size of SRAM leads to more stringent requirements for the deviation of circuit manufacturing process, and more sensitive to process fluctuations. Performance is also increasingly unstable. However, the market for high-speed and high-performance low-power SRAM demand is increasing. In order to meet the market demand of low power consumption, the technology of reducing power supply voltage has been proposed. However, the reduction of voltage will reduce the static noise tolerance of SRAM and further reduce the stability of SRAM. And with the increasing of the number of SRAM cells, the leakage power consumption can not be ignored in the static state. Especially for some systems where the leakage power is much larger than the dynamic power consumption, it is very important to reduce the leakage power to increase the battery life. In addition, for the traditional SRAM, the stored data will disappear after the system power off, and the information stored in the SRAM unit will be random when the power is switched on again, so the data stored before the power down cannot be recovered. This is no doubt not allowed for applications that need to preserve large amounts of field data and various system parameters. Although non-volatile memory has the ability to save data after power down, its slow speed can not replace the advantages of SRAM high speed, high performance and low power consumption. In order to preserve the advantage of SRAM on chip, many chips adopt "two-macro structure" two-macro structure, which contains volatile and non-volatile memory, and works in the same way as SRAM, and uses non-volatile memory to back up SRAM data when power is down. When power on again, the data before SRAM power down is written back to SRAM by non-volatile memory, so that the storage of SRAM power down information is realized and the advantages of high speed, high performance and low power consumption of SRAM are preserved. However, this method adopts verbatim transmission of data between volatile memory and nonvolatile memory. The speed of power down backup and power on recovery data is slow, and too long power off and power on time not only reduces the speed but also may cause data error. In order to reduce the power consumption of SRAM to complete SRAM power-down data storage, this paper presents several nonvolatile random access memory (RRAM) based on resistive random access memory (RRAM). The advantages and disadvantages of several schemes are compared and analyzed by simulation. Firstly, the size of the drive tube is adjusted to realize the predictable power state of SRAM. Because of increasing the size of each unit, the reduction of the area of each unit compared with the traditional 8T2R structure is not obvious, and the recovery rate of the scheme is lower than that of the traditional 8T2R structure. Then a predictable recovery scheme by interrupting the discharge path of SRAM is proposed, which saves a lot of chip area and improves the write-ability significantly, but the recovery rate is also low. Finally, a scheme to improve the performance of all aspects is put forward. The resistive nonvolatile memory cell consists of seven transistors and a resistive random access memory, including a non-volatile memory 1T1R) and a standard 6-transistor SRAM cell. The nonvolatile average 7T1RnvSRAMN NVA-7T1RN is constructed by adding a NMOS tube to each column of nvSRAM. Compared with the existing nvSRAM, the proposed scheme has the advantages of small area, high speed, low power consumption and strong reading and writing ability. The addition of a drop-down tail tube in each column greatly improves the unit writing ability, nearly twice as much as the traditional SRAM. In the stage of data recovery, because of breaking the latch of the SRAM coupling inverter, the recovery speed of the SRAM data is 2.5 times that of the previous 7T1R structure, and the DC power consumption of the unit is reduced by 63 times.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP333

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