本文選題：BCH碼 + 漢明碼��； 參考：《哈爾濱工業(yè)大學(xué)》2012年碩士論文

【摘要】：SoC中的存儲(chǔ)器在輻射環(huán)境中容易受到各種輻射效應(yīng)的影響。其中總劑量效應(yīng)和單粒子效應(yīng)對(duì)存儲(chǔ)器的影響最大。總劑量效應(yīng)使存儲(chǔ)器MOS管閾值電壓漂移、漏電增大，從而導(dǎo)致其電路速度降低、功耗增加甚至失效。單粒子效應(yīng)可能使存儲(chǔ)器發(fā)生硬錯(cuò)誤和軟錯(cuò)誤。隨著集成電路工藝的不斷進(jìn)步，特征尺寸不斷縮小，總劑量效應(yīng)對(duì)存儲(chǔ)器的影響在不斷減小，而存儲(chǔ)器由于單粒子效應(yīng)發(fā)生翻轉(zhuǎn)的概率卻越來(lái)越高。因此，在設(shè)計(jì)抗輻射SoC時(shí)可以采用錯(cuò)誤探測(cè)與糾正（EDAC）技術(shù)加固外部存儲(chǔ)器控制器（EMC），提高外部存儲(chǔ)器抗單粒子翻轉(zhuǎn)能力。 本文首先介紹線性分組碼理論，研究其編解碼電路實(shí)現(xiàn)方式，并采用修正漢明碼（39,32）和BCH碼設(shè)計(jì)錯(cuò)誤探測(cè)和糾正電路。修正漢明碼（39,32）能夠糾正任意一位錯(cuò)誤，并探測(cè)兩位錯(cuò)誤。采用該碼設(shè)計(jì)的錯(cuò)誤探測(cè)與糾正電路保護(hù)存儲(chǔ)在PROM中的數(shù)據(jù)。而加固SRAM的錯(cuò)誤探測(cè)與糾正電路采用BCH碼。本文使用的BCH碼為擴(kuò)展碼BCH（45,32），它能夠糾正任意兩位錯(cuò)誤，并探測(cè)三位錯(cuò)誤。由于編解碼電路應(yīng)用于外部存儲(chǔ)器，需要并行譯碼，因此本文采用查表譯碼方式實(shí)現(xiàn)譯碼。 在設(shè)計(jì)好編解碼電路的基礎(chǔ)上，本文研究了錯(cuò)誤探測(cè)與糾正電路的實(shí)現(xiàn)。由于對(duì)PROM加固的錯(cuò)誤探測(cè)與糾正電路結(jié)構(gòu)簡(jiǎn)單易于實(shí)現(xiàn)，，本文重點(diǎn)設(shè)計(jì)對(duì)SRAM加固的錯(cuò)誤探測(cè)與糾正電路。對(duì)SRAM加固的錯(cuò)誤探測(cè)與糾正電路，支持8位、16位和32位數(shù)據(jù)讀寫(xiě)操作。此外，它能夠糾正數(shù)據(jù)中任意兩位錯(cuò)誤，并能將糾正后的數(shù)據(jù)重新寫(xiě)入存儲(chǔ)器中避免軟錯(cuò)誤的積累。 最后，使用Verilog語(yǔ)言實(shí)現(xiàn)具有錯(cuò)誤探測(cè)與糾正功能的外部存儲(chǔ)器控制器，并搭建基于LEON3處理器SoC驗(yàn)證平臺(tái)對(duì)其進(jìn)行了系統(tǒng)驗(yàn)證，結(jié)果表明設(shè)計(jì)的電路能夠正常工作。
[Abstract]:Memory in SoC is vulnerable to various radiation effects in radiation environment. The total dose effect and single particle effect have the greatest effect on the memory. The total dose effect makes the threshold voltage drift and leakage increase in the memory MOS transistor, which leads to the decrease of the circuit speed, the increase of power consumption and even the failure of the circuit. Single particle effect may cause hard and soft errors in memory. With the development of integrated circuit technology, the characteristic size is shrinking and the total dose effect on the memory is decreasing. However, the probability of the memory turning over due to the single particle effect is higher and higher. Therefore, in the design of anti-radiation SoC, the technology of error detection and correction can be used to reinforce the external memory controller and improve the ability of external memory to resist single particle flipping. In this paper, the theory of linear block code is introduced, the realization of coding and decoding circuit is studied, and the error detection and correction circuit is designed by using modified Hanming code 39n32) and BCH code. Fixed hamming code 39 / 32) corrects any bit error and detects two-digit errors. The error detection and correction circuit designed by this code is used to protect the data stored in PROM. The BCH code is used in the error detection and correction circuit of the strengthened SRAM. The BCH code used in this paper is an extended code BCHF 45N 32, which can correct any two bit errors and detect three bit errors. Since the codec circuit is used in external memory, it needs parallel decoding, so this paper uses look-up table decoding method to realize decoding. Based on the design of codec circuit, the realization of error detection and correction circuit is studied in this paper. Because the structure of the error detection and correction circuit strengthened by PROM is simple and easy to realize, this paper focuses on the design of error detection and correction circuit for SRAM reinforcement. The error detection and correction circuit strengthened by SRAM supports 8 bit 16 bit and 32 bit data reading and writing operation. In addition, it can correct any two bit errors in the data and rewrite the corrected data to the memory to avoid the accumulation of soft errors. Finally, the external memory controller with the function of error detection and correction is realized by using Verilog language, and the system is verified based on the SoC verification platform of LEON3 processor. The results show that the designed circuit can work normally.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333

【參考文獻(xiàn)】

相關(guān)期刊論文 前3條

1 王一奇;趙發(fā)展;劉夢(mèng)新;呂蔭學(xué);趙博華;韓鄭生;;基于RHBD技術(shù)的深亞微米抗輻射SRAM電路的研究[J];半導(dǎo)體技術(shù);2012年01期

2 周定江;金明河;任偉;禹超;;基于LEON3的中央控制器設(shè)計(jì)及EDAC功能實(shí)現(xiàn)[J];機(jī)械與電子;2011年10期

3 賀興華;薛挺;肖山竹;盧煥章;;深亞微米CMOS SRAM SEE特性及加固技術(shù)研究[J];計(jì)算機(jī)工程與設(shè)計(jì);2009年12期

相關(guān)博士學(xué)位論文 前2條

1 孫巖;納米集成電路軟錯(cuò)誤分析與緩解技術(shù)研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2010年

2 龔銳;多核微處理器容軟錯(cuò)誤設(shè)計(jì)關(guān)鍵技術(shù)研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2008年

本文編號(hào)：1956068