本文選題：管道內(nèi)檢測(cè)器 + FPGA　； 參考：《天津大學(xué)》2012年碩士論文

【摘要】：管道運(yùn)輸作為一種安全、經(jīng)濟(jì)運(yùn)輸方式,被我國廣泛應(yīng)用于天然氣、石油等能源的運(yùn)輸。由于長時(shí)間的介質(zhì)腐蝕和磨損,運(yùn)輸管道會(huì)出現(xiàn)一定程度的損傷,甚至可能發(fā)生重大的泄漏事故。而管道運(yùn)輸?shù)陌踩P(guān)系著國家的經(jīng)濟(jì)及財(cái)產(chǎn)的安全,所以針對(duì)這種情況,管道內(nèi)檢測(cè)器的研究及發(fā)展就顯得尤為重要起來。 本文針對(duì)漏磁管道內(nèi)檢測(cè)器,采用當(dāng)今發(fā)展迅速的FPGA,利用其高速的并行處理能力,設(shè)計(jì)實(shí)現(xiàn)管道內(nèi)檢測(cè)數(shù)據(jù)的高速并行采集和存儲(chǔ)。首先,根據(jù)管道內(nèi)檢測(cè)器的外部結(jié)構(gòu),規(guī)劃出數(shù)據(jù)采集和存儲(chǔ)系統(tǒng)的總體設(shè)計(jì)方案,包括前端數(shù)據(jù)采集單元、中端數(shù)據(jù)傳輸單元和后端數(shù)據(jù)存儲(chǔ)單元;然后,根據(jù)系統(tǒng)的設(shè)計(jì)方案,介紹了系統(tǒng)中FPGA的選型、PCI接口實(shí)現(xiàn)方式、主控單片機(jī)的功能及電路、溫度記錄功能、姿態(tài)記錄功能以及FPGA的供電模塊設(shè)計(jì)和DCDC系統(tǒng)電源轉(zhuǎn)換模塊的選擇,系統(tǒng)地說明了系統(tǒng)中各功能的硬件實(shí)現(xiàn)方案。 根據(jù)本系統(tǒng)的硬件設(shè)計(jì),利用VerilogHDL語言編寫了包括集束器端FPGA和主控FPGA的各種接口模塊邏輯及緩存模塊邏輯,實(shí)現(xiàn)了16-5路SPI數(shù)據(jù)并行接收,5路LVDS串行收發(fā)器高速串行傳輸以及基于PCI9054的FPGA與PC104的PCI接口通訊,并根據(jù)接口協(xié)議之間不同的數(shù)據(jù)位寬或讀寫速度,結(jié)合乒乓操作等邏輯設(shè)計(jì)技巧,設(shè)計(jì)了相應(yīng)的緩存模塊,實(shí)現(xiàn)了不同接口之間的數(shù)據(jù)無縫緩沖。 針對(duì)系統(tǒng)中存在差分信號(hào)傳輸、PCI接口傳輸?shù)认鄬?duì)復(fù)雜的PCB設(shè)計(jì),分析討論了LVDS差分信號(hào)傳輸線及PCI接口信號(hào)傳輸線的PCB設(shè)計(jì)方法;根據(jù)系統(tǒng)結(jié)構(gòu),設(shè)計(jì)了集束器FPGA板卡、主控FPGA和上下連接信號(hào)板卡的PCB圖。 最后,對(duì)集束器FPGA與主探頭之間的SPI傳輸、主控FPGA與PC104之間的PCI傳輸進(jìn)行了硬件上的邏輯驗(yàn)證,驗(yàn)證了系統(tǒng)數(shù)據(jù)傳輸?shù)目煽啃?證明了FPGA實(shí)現(xiàn)高速數(shù)據(jù)采集存儲(chǔ)系統(tǒng)的可行性。
[Abstract]:As a safe and economical transportation mode, pipeline transportation is widely used in natural gas, petroleum and other energy transportation in China. Due to the corrosion and wear of medium for a long time, the transportation pipeline will be damaged to some extent, and even a serious leakage accident may occur. The safety of pipeline transportation is related to the national economy and property safety, so the research and development of pipeline detector is particularly important. In this paper, the high speed parallel acquisition and storage of the detection data in the pipeline is designed and realized by using the high speed parallel processing ability of FPGA, which is a rapidly developing FPGA. for the inner detector of magnetic flux leakage pipeline. Firstly, according to the external structure of the detector in the pipeline, the overall design scheme of the data acquisition and storage system is designed, including the front-end data acquisition unit, the mid-end data transmission unit and the back-end data storage unit. According to the design scheme of the system, this paper introduces the implementation mode of FPGA interface, the function and circuit of the main control MCU, the function of temperature record, the function of attitude record, the design of power supply module of FPGA and the choice of power conversion module of DCDC system. The hardware implementation scheme of each function in the system is explained systematically. According to the hardware design of the system, various interface module logic and buffer module logic including FPGA and FPGA are programmed by VerilogHDL language. The high speed serial transmission of 16-5 SPI data parallel receiving and 5-channel LVDS serial transceiver and the PCI interface communication between FPGA and PC104 based on PCI9054 are realized, and according to the different data bit width or read / write speed between the interface protocols, Combined with the logic design techniques such as ping-pong operation, the corresponding buffer module is designed to realize the seamless data buffering between different interfaces. In view of the relatively complex PCB design such as differential signal transmission and PCI interface transmission in the system, the PCB design method of LVDS differential signal transmission line and PCI interface signal transmission line is analyzed and discussed, and the FPGA card of the concentrator is designed according to the structure of the system. Main control FPGA and up and down connection signal board PCB diagram. Finally, the hardware logic verification of the SPI transmission between the FPGA and the main probe and the PCI transmission between the main control FPGA and the PC104 is carried out, the reliability of the system data transmission is verified, and the feasibility of realizing the high-speed data acquisition and storage system by FPGA is proved.
【學(xué)位授予單位】：天津大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333;TE973.6

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