本文選題：偽隨機(jī)數(shù)發(fā)生器 + 超素?cái)?shù)發(fā)生器　； 參考：《哈爾濱工程大學(xué)》2013年碩士論文

【摘要】：偽隨機(jī)數(shù)發(fā)生器在計(jì)算機(jī)仿真和信息安全領(lǐng)域都有著廣泛的用途，偽隨機(jī)數(shù)序列的隨機(jī)性、不可預(yù)測(cè)性以及產(chǎn)生速率對(duì)應(yīng)用系統(tǒng)的效率和安全性具有重要價(jià)值。本文設(shè)計(jì)了一種基于超素?cái)?shù)的組合式偽隨機(jī)數(shù)序列生成算法，并利用FPGA進(jìn)行了硬件實(shí)現(xiàn)和性能測(cè)試。 論文對(duì)偽隨機(jī)序列的產(chǎn)生原理、現(xiàn)有方法以及相關(guān)統(tǒng)計(jì)檢驗(yàn)方法和標(biāo)準(zhǔn)進(jìn)行了深入研究和討論分析。所提出的組合式算法首先通過(guò)時(shí)鐘計(jì)數(shù)器得到隨機(jī)的初始種子和參數(shù)，，之后利用超素?cái)?shù)發(fā)生器的特殊性質(zhì)，得到出現(xiàn)概率相同的“0”、“1”序列，再利用擾亂函數(shù)對(duì)“0”、“1”序列進(jìn)行擾亂重新排序，最后使用SHA_1安全散列算法完成對(duì)數(shù)列的進(jìn)一步發(fā)散，來(lái)增強(qiáng)序列的隨機(jī)性。本算法引入了不確定性和高速變換性因素，利用數(shù)據(jù)的奇偶性得到不規(guī)律的“0”、“1”序列，降低了生成數(shù)據(jù)之間的相關(guān)性，通過(guò)適時(shí)地改變發(fā)生器的相關(guān)參數(shù)，提高了偽隨機(jī)序列的周期。 為了對(duì)所提出的偽隨機(jī)數(shù)發(fā)生器的速度和統(tǒng)計(jì)特性進(jìn)行評(píng)估，利用Verilog HDL在FPGA上完成了算法的硬件實(shí)現(xiàn)，生成序列通過(guò)了FIPS140-2和NIST SP800-22兩個(gè)國(guó)際標(biāo)準(zhǔn)檢測(cè)集的所有項(xiàng)目檢驗(yàn)。實(shí)驗(yàn)結(jié)果表明所設(shè)計(jì)的偽隨機(jī)數(shù)發(fā)生器占用資源較少，產(chǎn)生的序列具有良好的隨機(jī)性,具有一定的實(shí)際應(yīng)用價(jià)值。
[Abstract]:Pseudorandom number generators are widely used in the field of computer simulation and information security. The randomness, unpredictability and production rate of pseudorandom number sequences are of great value to the efficiency and security of application systems. In this paper, a combined pseudorandom sequence generation algorithm based on superprime number is designed, and the hardware implementation and performance test are carried out by using FPGA. In this paper, the generation principle of pseudorandom sequence, the existing methods, and the relevant statistical test methods and standards are discussed and analyzed. The combined algorithm first obtains random initial seeds and parameters by clock counter, and then obtains "0" and "1" sequences with the same probability by using the special properties of superprime number generator. Then the "0" and "1" sequences are scrambled and reordered by the perturbation function. Finally, the further divergence of the sequence is accomplished by using the SHA_1 secure hash algorithm to enhance the randomness of the sequence. In this algorithm, uncertainty and high speed transformation are introduced, and the irregular "0" and "1" sequences are obtained by using the parity of data. The correlation between generated data is reduced, and the relevant parameters of generator are changed at the right time. The period of pseudorandom sequence is increased. In order to evaluate the speed and statistical characteristics of the proposed pseudorandom number generator, the hardware implementation of the algorithm is accomplished on FPGA with Verilog HDL, and the generated sequence is verified by all items of the two international standard detection sets, FIPS140-2 and NIST SP800-22. The experimental results show that the designed pseudorandom number generator occupies less resources and has good randomness and practical application value.
【學(xué)位授予單位】：哈爾濱工程大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP346

【參考文獻(xiàn)】

相關(guān)期刊論文 前9條

1 李世剛,劉輝,陳標(biāo)華;素?cái)?shù)的一個(gè)特殊性質(zhì)及其用于偽隨機(jī)數(shù)生成的方法[J];北京化工大學(xué)學(xué)報(bào)(自然科學(xué)版);2003年03期

2 李世剛,劉輝,陳標(biāo)華;超素?cái)?shù)法長(zhǎng)周期偽隨機(jī)數(shù)發(fā)生器的應(yīng)用算法[J];北京化工大學(xué)學(xué)報(bào)(自然科學(xué)版);2003年06期

3 薛之昕 ,王暹昊;數(shù)字簽名算法SHA-1的FPGA高速實(shí)現(xiàn)[J];今日電子;2004年03期

4 王萊,劉松強(qiáng);真隨機(jī)數(shù)發(fā)生器的設(shè)計(jì)和實(shí)現(xiàn)[J];核電子學(xué)與探測(cè)技術(shù);1998年06期

5 劉正高;標(biāo)準(zhǔn)均勻隨機(jī)數(shù)的產(chǎn)生方法分析[J];航天標(biāo)準(zhǔn)化;1996年05期

6 張傳軍;;隨機(jī)性及隨機(jī)提取器綜述[J];懷化學(xué)院學(xué)報(bào);2009年05期

7 王玉華;管愛(ài)紅;侯志強(qiáng);詹靜;張煥國(guó);;基于LFSR的演化隨機(jī)序列發(fā)生器[J];計(jì)算機(jī)工程;2009年06期

8 黃諄,白國(guó)強(qiáng),陳弘毅;快速實(shí)現(xiàn)SHA-1算法的硬件結(jié)構(gòu)[J];清華大學(xué)學(xué)報(bào)(自然科學(xué)版);2005年01期

9 曹潤(rùn)聰;曹立明;;Linux隨機(jī)數(shù)生成器的原理及缺陷[J];計(jì)算機(jī)技術(shù)與發(fā)展;2007年10期

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