本文選題：高速串行接口 + 千兆以太網(wǎng)��； 參考：《電子科技大學(xué)》2014年碩士論文

【摘要】：隨著用戶對(duì)信息傳輸需求的不斷增長(zhǎng),基帶信號(hào)處理的處理帶寬和吞吐量需求與日俱增。這對(duì)數(shù)據(jù)傳輸接口設(shè)計(jì)的要求越來(lái)越高,傳統(tǒng)的并行傳輸技術(shù)并不能滿足高帶寬、高速率和高可靠性的需求。此時(shí),高速串行傳輸技術(shù)應(yīng)運(yùn)而生,高速GTX接口和千兆以太網(wǎng)接口是其中兩個(gè)重要的數(shù)據(jù)傳輸接口�；谄暇W(wǎng)絡(luò)(NoC)的多核處理器硬件設(shè)計(jì)規(guī)模和復(fù)雜程度不斷增加,使得單片F(xiàn)PGA(或ASIC)硬件資源緊張的問(wèn)題突出。此外并行化處理機(jī)制將一個(gè)大的處理任務(wù)劃分為多個(gè)小的處理任務(wù),分配到不同的處理器上分別運(yùn)行,從而實(shí)現(xiàn)任務(wù)處理的并行化。這些都需要芯片間、處理器核間的高速數(shù)據(jù)傳遞。本論文利用高速串行接口實(shí)現(xiàn)了NoC互聯(lián)擴(kuò)展到多FPGA開(kāi)發(fā)板的總體設(shè)計(jì)。首先介紹了高速GTX接口的傳輸技術(shù)。接著在高速串行傳輸接口設(shè)計(jì)部分,對(duì)Aurora協(xié)議和用戶自定義通信協(xié)議進(jìn)行分析,并對(duì)二者做了簡(jiǎn)要的比較。最后,結(jié)合設(shè)計(jì)需求,本文采用了用戶自定義通信協(xié)議,并合理設(shè)計(jì)核間數(shù)據(jù)傳輸和狀態(tài)采集這兩種數(shù)據(jù)的幀格式,保證通道傳輸?shù)目煽啃耘c實(shí)時(shí)性。隨著互聯(lián)網(wǎng)技術(shù)不斷地創(chuàng)新和進(jìn)步,大量應(yīng)用的需求使得以太網(wǎng)傳輸模式迅速發(fā)展,基于以太網(wǎng)的小型嵌入式通信系統(tǒng)的應(yīng)用正變得越來(lái)越重要。千兆以太網(wǎng)作為第三代的以太網(wǎng)技術(shù),不僅保持了原來(lái)傳統(tǒng)以太網(wǎng)的優(yōu)勢(shì),還具有許多新的特性,因此得到了廣泛的應(yīng)用。本文介紹了千兆以太網(wǎng)傳輸技術(shù),對(duì)系統(tǒng)使用的PCS/PMA和三態(tài)MAC IP核進(jìn)行了研究和軟件仿真,完成了IP的設(shè)置和接口的設(shè)計(jì)。在驗(yàn)證平臺(tái)上進(jìn)行FPGA間、PC與FPGA間通過(guò)千兆以太網(wǎng)接口通信的實(shí)驗(yàn)測(cè)試時(shí),首先通過(guò)FPGA間的通信驗(yàn)證了接口代碼的正確性;再對(duì)通過(guò)BCM5396千兆以太網(wǎng)交換芯片連接FPGA和PC的場(chǎng)景進(jìn)行了測(cè)試,通過(guò)查看寄存器信息調(diào)試實(shí)現(xiàn)PC與FPGA間的正常通信。最后,在Xilinx Kirtex-7系列FPGA芯片為核心的硬件平臺(tái)上,完成了面向LTE公共基帶處理應(yīng)用的NoC原型實(shí)現(xiàn),對(duì)本文所設(shè)計(jì)的各個(gè)高速接口的功能和性能進(jìn)行了測(cè)試和驗(yàn)證。
[Abstract]:With the increasing demand of users for information transmission, the processing bandwidth and throughput of baseband signal processing are increasing. The traditional parallel transmission technology can not meet the requirements of high bandwidth, high speed and high reliability. At this time, high speed serial transmission technology came into being, high speed GTX interface and gigabit Ethernet interface are two important data transmission interfaces. The hardware design scale and complexity of multi-core processors based on on-chip network (NOC) are increasing, which makes the problem of single FPGA (or ASIC) hardware resource shortage prominent. In addition the parallel processing mechanism divides a large processing task into several small processing tasks and distributes them to different processors to realize the task processing parallelization. These require high-speed data transfer between chips and between processor cores. In this paper, a high-speed serial interface is used to realize the overall design of NoC interconnection to multi-FPGA development board. Firstly, the transmission technology of high speed GTX interface is introduced. Then, in the design of high-speed serial transmission interface, the paper analyzes the Aurora protocol and user-defined communication protocol, and makes a brief comparison between the two protocols. Finally, according to the design requirements, this paper adopts user-defined communication protocol, and reasonably designs the frame format of data transmission and state acquisition between cores to ensure the reliability and real-time of channel transmission. With the continuous innovation and progress of Internet technology, the demand of a large number of applications makes the Ethernet transmission mode develop rapidly. The application of small embedded communication system based on Ethernet is becoming more and more important. Gigabit Ethernet, as the third generation Ethernet technology, not only maintains the advantages of traditional Ethernet, but also has many new features, so it has been widely used. The transmission technology of gigabit Ethernet is introduced in this paper. The PCS/PMA and three-state MAC IP cores used in the system are studied and simulated, and the IP configuration and interface are designed. When we test the communication between FPGA PC and FPGA via Gigabit Ethernet interface on the verification platform, the correctness of the interface code is verified by the communication between FPGA and PC. The scene of connecting FPGA and PC through BCM5396 gigabit Ethernet switch chip is tested, and the normal communication between PC and FPGA is realized by checking register information. Finally, on the hardware platform of Xilinx Kirtex-7 series FPGA chips, the NoC prototype for LTE common baseband processing application is implemented, and the function and performance of each high-speed interface designed in this paper are tested and verified.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TP393.11;TP334.7

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本文編號(hào)：1927894