本文選題：高速串行接口 + 千兆以太網�。� 參考：《電子科技大學》2014年碩士論文

【摘要】：隨著用戶對信息傳輸需求的不斷增長,基帶信號處理的處理帶寬和吞吐量需求與日俱增。這對數據傳輸接口設計的要求越來越高,傳統(tǒng)的并行傳輸技術并不能滿足高帶寬、高速率和高可靠性的需求。此時,高速串行傳輸技術應運而生,高速GTX接口和千兆以太網接口是其中兩個重要的數據傳輸接口�；谄暇W絡(NoC)的多核處理器硬件設計規(guī)模和復雜程度不斷增加,使得單片FPGA(或ASIC)硬件資源緊張的問題突出。此外并行化處理機制將一個大的處理任務劃分為多個小的處理任務,分配到不同的處理器上分別運行,從而實現任務處理的并行化。這些都需要芯片間、處理器核間的高速數據傳遞。本論文利用高速串行接口實現了NoC互聯擴展到多FPGA開發(fā)板的總體設計。首先介紹了高速GTX接口的傳輸技術。接著在高速串行傳輸接口設計部分,對Aurora協(xié)議和用戶自定義通信協(xié)議進行分析,并對二者做了簡要的比較。最后,結合設計需求,本文采用了用戶自定義通信協(xié)議,并合理設計核間數據傳輸和狀態(tài)采集這兩種數據的幀格式,保證通道傳輸的可靠性與實時性。隨著互聯網技術不斷地創(chuàng)新和進步,大量應用的需求使得以太網傳輸模式迅速發(fā)展,基于以太網的小型嵌入式通信系統(tǒng)的應用正變得越來越重要。千兆以太網作為第三代的以太網技術,不僅保持了原來傳統(tǒng)以太網的優(yōu)勢,還具有許多新的特性,因此得到了廣泛的應用。本文介紹了千兆以太網傳輸技術,對系統(tǒng)使用的PCS/PMA和三態(tài)MAC IP核進行了研究和軟件仿真,完成了IP的設置和接口的設計。在驗證平臺上進行FPGA間、PC與FPGA間通過千兆以太網接口通信的實驗測試時,首先通過FPGA間的通信驗證了接口代碼的正確性;再對通過BCM5396千兆以太網交換芯片連接FPGA和PC的場景進行了測試,通過查看寄存器信息調試實現PC與FPGA間的正常通信。最后,在Xilinx Kirtex-7系列FPGA芯片為核心的硬件平臺上,完成了面向LTE公共基帶處理應用的NoC原型實現,對本文所設計的各個高速接口的功能和性能進行了測試和驗證。
[Abstract]:With the increasing demand of users for information transmission, the processing bandwidth and throughput of baseband signal processing are increasing. The traditional parallel transmission technology can not meet the requirements of high bandwidth, high speed and high reliability. At this time, high speed serial transmission technology came into being, high speed GTX interface and gigabit Ethernet interface are two important data transmission interfaces. The hardware design scale and complexity of multi-core processors based on on-chip network (NOC) are increasing, which makes the problem of single FPGA (or ASIC) hardware resource shortage prominent. In addition the parallel processing mechanism divides a large processing task into several small processing tasks and distributes them to different processors to realize the task processing parallelization. These require high-speed data transfer between chips and between processor cores. In this paper, a high-speed serial interface is used to realize the overall design of NoC interconnection to multi-FPGA development board. Firstly, the transmission technology of high speed GTX interface is introduced. Then, in the design of high-speed serial transmission interface, the paper analyzes the Aurora protocol and user-defined communication protocol, and makes a brief comparison between the two protocols. Finally, according to the design requirements, this paper adopts user-defined communication protocol, and reasonably designs the frame format of data transmission and state acquisition between cores to ensure the reliability and real-time of channel transmission. With the continuous innovation and progress of Internet technology, the demand of a large number of applications makes the Ethernet transmission mode develop rapidly. The application of small embedded communication system based on Ethernet is becoming more and more important. Gigabit Ethernet, as the third generation Ethernet technology, not only maintains the advantages of traditional Ethernet, but also has many new features, so it has been widely used. The transmission technology of gigabit Ethernet is introduced in this paper. The PCS/PMA and three-state MAC IP cores used in the system are studied and simulated, and the IP configuration and interface are designed. When we test the communication between FPGA PC and FPGA via Gigabit Ethernet interface on the verification platform, the correctness of the interface code is verified by the communication between FPGA and PC. The scene of connecting FPGA and PC through BCM5396 gigabit Ethernet switch chip is tested, and the normal communication between PC and FPGA is realized by checking register information. Finally, on the hardware platform of Xilinx Kirtex-7 series FPGA chips, the NoC prototype for LTE common baseband processing application is implemented, and the function and performance of each high-speed interface designed in this paper are tested and verified.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP393.11;TP334.7

【參考文獻】

相關期刊論文 前1條

1 汪健;張磊;趙忠惠;王少軒;陳亞寧;;多核系統(tǒng)中NoC通訊架構的關鍵技術[J];電子科技;2012年06期

相關碩士學位論文 前1條

1 潘國禎;基于FPGA實現的高速串口傳輸技術與實現[D];復旦大學;2009年

，

本文編號：1927894