本文選題：交換接口 + 網(wǎng)絡(luò)處理器�。� 參考：《西安電子科技大學(xué)》2013年碩士論文

【摘要】：隨著網(wǎng)絡(luò)系統(tǒng)的高速發(fā)展，，作為網(wǎng)絡(luò)系統(tǒng)的核心設(shè)備網(wǎng)絡(luò)處理器也得到了高速的發(fā)展，高速數(shù)據(jù)交換接口的性能是網(wǎng)絡(luò)處理器處理網(wǎng)絡(luò)數(shù)據(jù)包和影響網(wǎng)絡(luò)處理器性能的關(guān)鍵因素之一，而且它和MAC芯片之間的交換接口性能決定著網(wǎng)絡(luò)處理器最大的數(shù)據(jù)吞吐能力，所以設(shè)計實現(xiàn)網(wǎng)絡(luò)處理器中高速數(shù)據(jù)交換接口對于提升整個網(wǎng)絡(luò)的性能就顯得意義特別重大。 本文重點研究了網(wǎng)絡(luò)處理器中高速數(shù)據(jù)交換接口的幾點關(guān)鍵技術(shù)的解決方案。為了實現(xiàn)MAC設(shè)備與網(wǎng)絡(luò)處理器之間數(shù)據(jù)包的高速傳輸，將不需要微處理引擎處理的數(shù)據(jù)包凈荷部分通過DMA通道存儲到片外SDRAM存儲器；MAC芯片和網(wǎng)絡(luò)處理器的通信由于工作頻率或者相位的不同，采用雙口SRAM存儲器作為數(shù)據(jù)緩存；為了保證發(fā)送數(shù)據(jù)的可靠性，采用兩個有效標(biāo)志位置位的方式確保數(shù)據(jù)能夠高效可靠的發(fā)送到外部MAC設(shè)備；當(dāng)高速數(shù)據(jù)交換接口與外接10/100M的MAC設(shè)備進(jìn)行通信時，采用輪詢的方式來獲取MAC設(shè)備中FIFO數(shù)據(jù)的就緒狀態(tài)；當(dāng)高速數(shù)據(jù)交換接口與1000M的MAC設(shè)備進(jìn)行通信時，采用主動請求機制接收數(shù)據(jù)包。 對高速數(shù)據(jù)交換接口采用自頂向下的方法進(jìn)行具體的設(shè)計，通過模塊劃分完成結(jié)構(gòu)設(shè)計，對每個模塊的具體特點進(jìn)行詳細(xì)描述，使用Verilog硬件描述語言完成高速數(shù)據(jù)交換接口的RTL級設(shè)計。對常用的驗證方法進(jìn)行介紹，并對設(shè)計的高速數(shù)據(jù)交換接口進(jìn)行功能驗證，然后給出適合本設(shè)計的驗證方案，在此方案的基礎(chǔ)上通過對需要驗證的各項功能進(jìn)行一致性對比，通過一套較完善的手段來檢查設(shè)計的功能正確性。制定了性能評估方案，介紹性能測試的方法，然后對性能測試結(jié)果進(jìn)行評估，最后對高速數(shù)據(jù)交換接口進(jìn)行邏輯實現(xiàn)。得到了高速數(shù)據(jù)交換接口的面積和最大工作頻率。
[Abstract]:With the rapid development of network system, network processor, the core device of network system, has also been developed rapidly. The performance of high-speed data exchange interface is one of the key factors for network processor to process network data packets and affect the performance of network processor. Moreover, the performance of switching interface between network processor and MAC chip determines the maximum data throughput of network processor. So it is very important to design and implement the high-speed data exchange interface in the network processor to improve the performance of the whole network. This paper focuses on the solution of several key technologies of high-speed data exchange interface in network processor. In order to realize the high-speed transmission of data packets between MAC devices and network processors, The data packet payload part which does not need to be processed by the micro-processing engine is stored to the off-chip SDRAM memory DMA chip and the network processor through the DMA channel. Because of the different operating frequency or phase, the dual-port SRAM memory is used as the data cache. In order to ensure the reliability of transmitting data, two effective marking position bits are adopted to ensure that the data can be transmitted to external MAC devices efficiently and reliably. When the high-speed data exchange interface communicates with the 10 / 100m external MAC devices, The ready state of FIFO data in MAC devices is obtained by polling, and when the high-speed data exchange interface communicates with 1000M MAC devices, the active request mechanism is used to receive data packets. The top-down method is used to design the high-speed data exchange interface. The structure is designed by module partition, and the specific characteristics of each module are described in detail. Verilog hardware description language is used to complete the RTL level design of high speed data exchange interface. The common verification methods are introduced, and the function of the designed high-speed data exchange interface is verified. Then the verification scheme suitable for this design is given. On the basis of this scheme, the consistency of the functions that need to be verified is compared. Through a set of more perfect means to check the functional correctness of the design. The performance evaluation scheme is established, the method of performance testing is introduced, and the performance test results are evaluated. Finally, the logical implementation of the high-speed data exchange interface is carried out. The area and maximum working frequency of high speed data exchange interface are obtained.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP334.7

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