發(fā)布時間：2018-05-20 17:15

  本文選題：PCI接口 + PCI2.2協(xié)議��； 參考：《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：YHFT-DSPX是我校自主設(shè)計(jì)的新一代高性能32位定點(diǎn)DSP微處理器芯片，在無線基站、ADSL、雷達(dá)、圖像及多媒體信息處理等高性能數(shù)字信號處理方面應(yīng)用前景廣泛。本文為YHFT-DSPX設(shè)計(jì)實(shí)現(xiàn)了一款32位的PCI接口，以增強(qiáng)DSP與外部主機(jī)以及與外圍控制部件的數(shù)據(jù)傳輸能力，為DSP與主機(jī)之間的數(shù)據(jù)通信提供了快速通道。 本文深入分析PCI接口的功能特點(diǎn)，按YHFT-DSPX系統(tǒng)要求完成了PCI接口的設(shè)計(jì)驗(yàn)證和FPGA仿真。所設(shè)計(jì)的PCI接口部件基于PCI2.2總線協(xié)議并滿足PC99規(guī)范要求，總線寬度32位，PCI工作頻率33MHz，最高傳輸帶寬可達(dá)132MB/s。接口支持存儲器讀、存儲器一行讀、存儲器多行讀、存儲器寫、IO讀、IO寫、配置寄存器讀以及配置寄存器寫等PCI總線命令。接口可作為發(fā)起總線事務(wù)主設(shè)備也可作為接受總線事務(wù)的從設(shè)備。接口具備自動初始化功能：外接EEPROM存儲器，在PCI接口上電復(fù)位后，EEPROM控制器用ROM中存儲的配置信息自動完成PCI接口的初始化配置。接口內(nèi)部通過DMA傳輸和DSP連接，使用多個并行的FIFO來保證接口的高速數(shù)據(jù)傳輸。另外，PCI接口內(nèi)部有專門的寄存器文件通道和DSP連接，方便DSP和PCI接口之間進(jìn)行狀態(tài)信息和控制命令的交互。 最后論文對PCI接口部件采用65nm標(biāo)準(zhǔn)單元工藝庫進(jìn)行了綜合，，接口內(nèi)部時鐘最高工作頻率可以達(dá)到555MHz。按照系統(tǒng)最低400MHz的內(nèi)部時鐘工作頻率要求，PCI接口綜合結(jié)果面積為61781um~2，功耗為3.1696mW。符合系統(tǒng)設(shè)計(jì)要求。
[Abstract]:YHFT-DSPX is a new generation of high performance 32-bit fixed-point DSP microprocessor designed by our university. It has a wide application prospect in wireless base station, radar, image and multimedia information processing and other high-performance digital signal processing. In this paper, a 32-bit PCI interface is designed and implemented for YHFT-DSPX to enhance the ability of data transmission between DSP and external host and peripheral control components, and to provide a fast channel for data communication between DSP and host. In this paper, the functional characteristics of PCI interface are deeply analyzed, and the design and verification of PCI interface and FPGA simulation are completed according to the requirements of YHFT-DSPX system. The designed PCI interface is based on the PCI2.2 bus protocol and meets the requirements of the PC99 specification. The bus width is 32 bits and the operating frequency is 33MHz. The maximum transmission bandwidth can be up to 132MB / s. The interface supports memory reading, memory line reading, memory multiline reading, memory writing IO reading, configuration register writing and other PCI bus commands. The interface can act as the host device for initiating a bus transaction or as a slave device for receiving a bus transaction. Interface has the function of automatic initialization: external EEPROM memory, after the PCI interface power reset, the EEPROM controller automatically completes the initialization configuration of PCI interface with the configuration information stored in ROM. The interface is connected by DMA and DSP, and multiple parallel FIFO are used to guarantee the high speed data transmission of the interface. In addition, there is a special register file channel and DSP connection inside the interface, which facilitates the exchange of state information and control commands between DSP and PCI interface. Finally, the 65nm standard cell process library is used to synthesize the PCI interface components. The highest working frequency of the internal clock can reach 555MHz. According to the minimum internal clock frequency of the system, the integrated result area of 400MHz interface is 61781 umm2, and the power consumption is 3.1696 MW. Meet the system design requirements.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP334.7

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