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基于FPGA與DDR2的視頻緩存器設計與實現(xiàn)

發(fā)布時間:2018-05-20 01:28

  本文選題:邊緣調制器 + FPGA; 參考:《成都理工大學》2012年碩士論文


【摘要】:隨著信息技術的不斷發(fā)展,嵌入式系統(tǒng)被應用于越來越廣泛的領域。在視頻系統(tǒng)中高速大容量緩存器被廣泛應用,然而專用高速大容量的緩存芯片價格過于昂貴,傳統(tǒng)存儲媒介在帶寬上已經逐漸無法滿足使用要求,特別是對于海量多路數據多進多出時性能上更加難以得到保障。 近幾年以來隨著數字電視技術的不斷發(fā)展,大量的數據需要傳播。所以在使用視頻系統(tǒng)進行數據處理時,就需要能在容量和速度上與之相適應的存儲器作為高速海量緩存的載體。因為FPGA能進行現(xiàn)場設計且設計的靈活性強,而DDR2SDRAM有著存儲速度快、存儲容量大以及價格便宜的優(yōu)勢,所以兩者已經被廣泛的應用于各個領域,而在視頻系統(tǒng)的設計應用中也越來越多的受到了關注。本文主要研究了基于FPGA和DDR2SDRAM的高速視頻緩存技術,為高速多通道的存儲設計提出了新的思路。在本論文里首先介紹了IPQAM系統(tǒng)的相關研究情況,并對FPGA和DDR2SDRAM工作特性、功能、設計要求逐一闡述,然后通過對Xilinx公司的FPGA和DDR2SDRAM存儲原理的研究,提出了能夠應用于IPQAM系統(tǒng)的改進型MIMO結構的視頻存儲方案,,滿足了多通道數據存儲的指標要求。 本文利用FPGA和DDR2SDRAM存儲器件實現(xiàn)了多路數據多進多出的存儲方案,并可以應用在基于DVB-C的IPQAM調制器系統(tǒng)中,滿足其高速、海量、多通道存儲的要求。并通過Xilinx的Spartan3FPGA器件實現(xiàn)了DDR2內存接口的控制。通過使用Xilinx提供的DDR2IP核和參考用例,大大降低了接口設計的難度并且提高了整個設計的可靠性。在本設計中已對所有單元模塊進行了設計、編程并經過了仔細的功能仿真和時序分析,測試結果表明整個設計達到了系統(tǒng)要求,確保了緩存器在IPQAM系統(tǒng)中的工作可靠性。取得的具體成果如下: (1)在FPGA的核心邏輯設計中,采用了無線通信系統(tǒng)中的多徑傳輸理論對系統(tǒng)總體架構進行設計。 (2)本設計實現(xiàn)了一種具有FIFO特性的存儲介質接口裝置,便捷了對復雜時序接口的大容量、多通道、高速存儲介質的應用。 (3)本設計滿足了IPQAM設備中對于數據存儲的要求,實現(xiàn)了消除視頻信號網絡抖動的目的。
[Abstract]:With the development of information technology, embedded system is applied in more and more fields. High-speed and high-capacity buffers are widely used in video systems. However, the cost of dedicated high-speed and high-capacity buffer chips is too high, the traditional storage media has been unable to meet the requirements in bandwidth. Especially, it is more difficult to guarantee the performance of mass multiplex data when multi-input and multi-output. In recent years, with the development of digital television technology, a large number of data need to be disseminated. Therefore, when we use video system to process data, we need the memory which can adapt to the capacity and speed as the carrier of mass cache. Because FPGA can carry out field design and design flexibility, and DDR2SDRAM has the advantages of high storage speed, large storage capacity and low price, both of them have been widely used in various fields. More and more attention has been paid to the design and application of video system. This paper mainly studies the technology of high-speed video cache based on FPGA and DDR2SDRAM, and puts forward a new idea for the design of high-speed multi-channel storage. In this paper, we first introduce the research situation of IPQAM system, and describe the working characteristics, functions and design requirements of FPGA and DDR2SDRAM one by one, and then through the research of FPGA and DDR2SDRAM storage principle of Xilinx Company. A video storage scheme based on improved MIMO structure for IPQAM system is proposed, which meets the requirements of multi-channel data storage. In this paper, FPGA and DDR2SDRAM memory devices are used to realize multi-channel data multi-input and multi-output storage, which can be applied to IPQAM modulator system based on DVB-C, which can meet the requirements of high-speed, massive and multi-channel storage. The control of DDR2 memory interface is realized by Spartan3FPGA device of Xilinx. By using the DDR2IP core and reference case provided by Xilinx, the difficulty of interface design is greatly reduced and the reliability of the whole design is improved. In this design, all the unit modules have been designed and programmed, and after careful functional simulation and timing analysis, the test results show that the whole design meets the requirements of the system and ensures the reliability of the buffer in the IPQAM system. The following concrete results have been achieved: In the core logic design of FPGA, the multipath transmission theory in wireless communication system is adopted to design the overall architecture of the system. In this paper, a storage medium interface device with FIFO characteristics is designed and implemented, which facilitates the application of large capacity, multi-channel and high speed storage media to complex sequential interfaces. The design meets the requirement of data storage in IPQAM equipment and realizes the purpose of eliminating the network jitter of video signal.
【學位授予單位】:成都理工大學
【學位級別】:碩士
【學位授予年份】:2012
【分類號】:TP333;TN791

【參考文獻】

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