發(fā)布時間：2018-05-17 06:35

  本文選題：浮點加法 + 雙通道算法��； 參考：《南京航空航天大學》2012年碩士論文

【摘要】：隨著信息應用領域?qū)?shù)據(jù)運算精度要求的不斷提高和數(shù)值運算范圍的不斷擴大，現(xiàn)代微處理器中，浮點運算單元（Floating-point Unit，F(xiàn)PU）的研究顯得越來越重要。根據(jù)相關技術報告，浮點運算中55%以上是浮點加法運算。因此，浮點加法是使用頻率最高的浮點運算，浮點加法器也成為微處理器、現(xiàn)代信號處理系統(tǒng)中最重要的部件之一。IEEE-754標準中浮點數(shù)定義的復雜性使得硬件實現(xiàn)浮點加法操作的速度遠低于定點數(shù)。 本文在傳統(tǒng)浮點加法器串行計算結(jié)構的基礎上，討論了并行計算的雙通道算法，改進的雙通道算法等結(jié)構。在雙通道結(jié)構中，，分析研究前導1（前導0）預測算法，桶形移位器等關鍵結(jié)構和模塊。在深入研究和分析這些關鍵結(jié)構和模塊之后，總體上確定了以雙通道算法為本文所設計的浮點加法器的結(jié)構。在前導1預測的模塊中，以預編碼邏輯為基礎，對預編碼進行前導1檢測。此外，移位器使用純組合邏輯電路的桶形移位器，以避免使用移位寄存器邏輯電路所帶來的延時。 定點加法器作為浮點加法運算中不可或缺的模塊之一，很大程度上制約著浮點加法器的性能。本文在定點加法器部分，在傳統(tǒng)并行前綴加法器原有的結(jié)構基礎上，介紹了一種高速的Ling進位加法器，并且提出了一種基于Ling加法器的邏輯電路層次結(jié)構上的改進的加法器。實驗數(shù)據(jù)表明，本文設計的改進32位Ling加法器比傳統(tǒng)32位并行前綴Ling加法器延時降低了約18%，同時面積上也減小了20%左右。本文使用一個24位的改進Ling加法器用于浮點加法器的尾數(shù)運算模塊中，使得優(yōu)化后的浮點加法器延時進一步減小。 論文完成了浮點加法器從體系結(jié)構選擇、算法研究到可綜合的代碼編寫、仿真綜合等一系列工作。所有的設計均使用VerilogHDL語言作為設計輸入，所有的數(shù)據(jù)均在Synopsys的DC下進行綜合得到。實驗結(jié)果表明，本文設計的浮點加法器可以高效地、正確地完成浮點加法運算，達到了預期的目標。
[Abstract]:With the improvement of the precision of data operation and the expansion of numerical operation range in the field of information application, the research of floating-point unit (Floating-point unit FPU) is becoming more and more important in modern microprocessors. According to relevant technical reports, more than 55% of floating-point operations are floating-point addition operations. Therefore, floating-point addition is a floating-point operation with the highest frequency, and the floating-point adder becomes a microprocessor. The complexity of floating-point definition in IEEE-754 standard makes the speed of floating-point addition in hardware much lower than the number of fixed points. Based on the serial computing structure of the traditional floating-point adder, this paper discusses the two-channel algorithm for parallel computing and the improved two-channel algorithm for parallel computing. In the dual channel structure, the key structures and modules, such as preamble 1 (lead 0) prediction algorithm, bucket shifter and so on, are analyzed and studied. After deeply studying and analyzing these key structures and modules, the structure of the floating-point adder designed in this paper based on the two-channel algorithm is determined. In the precoding 1 prediction module, precoding logic is used to detect the precoding. In addition, the shifter uses a bucket shifter of pure combinational logic circuits to avoid the delay caused by the use of shift register logic circuits. As one of the indispensable modules in floating-point addition, fixed-point adder restricts the performance of floating-point adder to a great extent. In the part of fixed-point adder, this paper introduces a high-speed Ling carry adder based on the original structure of traditional parallel prefix adder, and proposes an improved adder based on Ling adder in logic circuit hierarchy. The experimental data show that the improved 32-bit Ling adder can reduce the delay time by about 18% and reduce the area by about 20% compared with the traditional 32-bit parallel prefix Ling adder. In this paper, a 24-bit improved Ling adder is used in the Mantissa calculation module of the floating-point adder, which further reduces the delay of the optimized floating-point adder. In this paper, a series of tasks, such as architecture selection, algorithm research, compositive coding, simulation synthesis and so on, are completed. All the designs use VerilogHDL language as the design input, and all the data are synthesized under the DC of Synopsys. The experimental results show that the floating-point adder designed in this paper can accomplish floating-point addition efficiently and correctly, and achieve the desired goal.
【學位授予單位】：南京航空航天大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332.21

【參考文獻】

相關期刊論文 前4條

1 崔曉平;王成華;;二級進位跳躍加法器的優(yōu)化方塊分配[J];北京航空航天大學學報;2007年04期

2 楊靚,徐煒,黃士坦;FPGA上浮點加/減法器的設計[J];計算機工程與應用;2003年02期

3 崔曉平;王成華;;快速靜態(tài)進位跳躍加法器[J];南京理工大學學報(自然科學版);2007年01期

4 夏杰;宣志斌;薛忠杰;;基于流水線結(jié)構的浮點加法器IP核設計[J];微計算機信息;2008年27期

相關博士學位論文 前1條

1 孫海平;計算機算術中若干前綴計算問題的研究[D];合肥工業(yè)大學;2006年

相關碩士學位論文 前4條

1 靳戰(zhàn)鵬;高速浮點加法運算單元的研究與實現(xiàn)[D];西北工業(yè)大學;2006年

2 李兆亮;“銀河飛騰”DSP的ALU單元全定制設計優(yōu)化[D];國防科學技術大學;2006年

3 黎淵;高性能浮點乘、加部件的研究與實現(xiàn)[D];國防科學技術大學;2008年

4 陳芳園;浮點處理單元設計關鍵技術研究與實現(xiàn)[D];國防科學技術大學;2008年

本文編號：1900353