本文選題：NAND + Flash陣列　； 參考：《中國科學(xué)院研究生院（光電技術(shù)研究所）》2013年博士論文

【摘要】：NAND Flash具有功耗低、體積小、重量輕、固態(tài)化、發(fā)熱少、抗震能力強、工作溫度寬等優(yōu)點，非常適合用來設(shè)計使用環(huán)境嚴(yán)酷的超高速圖像記錄系統(tǒng)。本文針對基于NAND Flash設(shè)計記錄系統(tǒng)存在的一系列關(guān)鍵技術(shù)問題，，分別提出和實現(xiàn)了滿足高性能要求的系統(tǒng)架構(gòu)和數(shù)據(jù)流控制算法。 針對如何提高NAND Flash物理底層訪問速度問題，研究了NAND Flash的內(nèi)部結(jié)構(gòu)和工作原理，分析了各類操作的物理底層驅(qū)動邏輯。在FPGA中分別實現(xiàn)了操作NAND Flash的各種時序。從理論層面研究了傳統(tǒng)的片外流水線和并行技術(shù)，并提出了片外兩級流水和內(nèi)部交叉寫入結(jié)合的方法。通過FPGA硬件實現(xiàn)，證明了本文提出的方法具有最大流水線加速比，能有效提高寫入速度，同時減少了FPGA引腳資源占用。 針對壞塊表的快速檢索和可靠存儲問題，提出了基于位索引的壞塊信息快速檢索結(jié)構(gòu)；為解決壞塊快速匹配問題，提出了基于滑動窗口的無效塊預(yù)匹配機(jī)制；對于突發(fā)壞塊造成寫入速度下降問題，提出了滯后回寫機(jī)制。壞塊管理全部用硬件實現(xiàn)；提出并實現(xiàn)了一種高效的并適合于順序數(shù)據(jù)流記錄的損耗均衡方法。同時提出和實現(xiàn)了一種NAND Flash擴(kuò)展方法，能有效避免NAND Flash記錄系統(tǒng)要使用多個NAND Flash控制器的情況，節(jié)省了FPGA內(nèi)部資源； 針對嵌入式超高速圖像記錄應(yīng)用中，任務(wù)如何有效管理的問題，設(shè)計了超高速圖像數(shù)據(jù)流內(nèi)存緩存機(jī)制，實現(xiàn)了高帶寬圖像數(shù)據(jù)緩存和任務(wù)附加信息實時嵌入。提出了一種兩級數(shù)據(jù)索引機(jī)制，并詳細(xì)闡述了任務(wù)管理的映射關(guān)系。為保證記錄數(shù)據(jù)的安全性，實現(xiàn)了任務(wù)管理相關(guān)表項在NOR Flash中的備份和定時更新機(jī)制。實踐表明，以上方法能夠有效降低CPU開銷，適合在嵌入式系統(tǒng)中應(yīng)用。 針對記錄系統(tǒng)性能測試問題，設(shè)計了測試模型，包括：針對系統(tǒng)可靠性初步測試問題，設(shè)計了基于指數(shù)回歸的速度壓力模型和基于對數(shù)正態(tài)分布的測試時長控制模型；針對峰值記錄速度測定問題，提出了基于爬山搜索算法和速率二分法的軟硬件協(xié)同測試方法。通過FPGA實現(xiàn)，驗證了提出方法的有效性。 為了推進(jìn)相關(guān)研究成果的工程實用化，設(shè)計并實現(xiàn)了光電經(jīng)緯儀NANDFlash嵌入式圖像記錄系統(tǒng)。分別研究和實現(xiàn)了光纖、PCIE、千兆網(wǎng)傳輸、DVI顯示回放以及基于WEB服務(wù)器的記錄系統(tǒng)遠(yuǎn)程管理技術(shù)。結(jié)果表明，該系統(tǒng)最大記錄帶寬可達(dá)1260MB/s，容量可達(dá)8TB；最后，研究了結(jié)構(gòu)緊湊多模塊記錄系統(tǒng)，設(shè)計了3U CPCIE記錄模塊。該系統(tǒng)可根據(jù)具體需求增加和裁剪記錄模塊，實現(xiàn)不同的記錄性能。
[Abstract]:NAND Flash has the advantages of low power consumption, small volume, light weight, solid state, less heating, strong seismic ability, wide working temperature, etc., so it is very suitable for designing ultra-high speed image recording system with harsh environment. Aiming at a series of key technical problems existing in the design of recording system based on NAND Flash, this paper proposes and implements the system architecture and data flow control algorithm which meet the requirements of high performance respectively. Aiming at the problem of how to improve the access speed of physical bottom layer of NAND Flash, the internal structure and working principle of NAND Flash are studied, and the physical underlying driving logic of all kinds of operations is analyzed. All kinds of timing of NAND Flash operation are realized in FPGA. In this paper, the traditional off-chip pipeline and parallel technology are studied theoretically, and the method of combining two-stage pipeline and internal cross-writing is proposed. Through the implementation of FPGA hardware, it is proved that the proposed method has the maximum pipeline speedup ratio, can effectively improve the write speed and reduce the FPGA pin resource consumption. In order to solve the problem of fast retrieval and reliable storage of bad block table, a fast retrieval structure of bad block information based on bit index is proposed, and an invalid block pre-matching mechanism based on sliding window is proposed to solve the problem of fast bad block matching. For the problem of slow down of writing speed caused by burst bad block, a delayed write-back mechanism is proposed. The bad block management is implemented by hardware, and an efficient loss equalization method suitable for sequential data stream recording is proposed and implemented. At the same time, a NAND Flash extension method is proposed and implemented, which can effectively avoid the use of multiple NAND Flash controllers in the NAND Flash recording system and save the internal resources of FPGA. Aiming at the problem of how to manage the task effectively in the application of embedded ultra high speed image recording, a memory cache mechanism of super high speed image data stream is designed, which realizes the high bandwidth image data cache and the real time embedding of task additional information. A two-level data indexing mechanism is proposed and the mapping relationship of task management is described in detail. In order to ensure the security of recording data, the backup and timing updating mechanism of task management related table items in NOR Flash is implemented. Practice shows that the above method can effectively reduce the CPU overhead and is suitable for application in embedded systems. Aiming at the problem of recording system performance test, the test model is designed, including: aiming at the system reliability preliminary test problem, the speed pressure model based on exponential regression and the test time control model based on logarithmic normal distribution are designed. In order to solve the problem of peak recording speed measurement, a software / hardware co-testing method based on mountain climbing search algorithm and rate dichotomy is proposed. The effectiveness of the proposed method is verified by FPGA implementation. In order to promote the engineering practicability of related research results, an embedded image recording system for photoelectric theodolite NANDFlash is designed and implemented. The technologies of optical fiber PCIEs, Gigabit network transmission DVI display and playback and remote management of recording system based on WEB server are studied and implemented respectively. The results show that the maximum recording bandwidth of the system can reach 1260 MBs and the capacity can reach 8 TB.Finally, the compact multi-module recording system is studied, and the 3U CPCIE recording module is designed. The system can add and cut the recording module according to the specific requirements to achieve different recording performance.
【學(xué)位授予單位】：中國科學(xué)院研究生院（光電技術(shù)研究所）
【學(xué)位級別】：博士
【學(xué)位授予年份】：2013
【分類號】：TP333;TP391.41

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本文編號：1894456