本文選題：PCIE + 信號完整性��； 參考：《北京郵電大學(xué)》2013年碩士論文

【摘要】：隨著微處理器技術(shù)、多媒體技術(shù)與網(wǎng)絡(luò)技術(shù)的迅速發(fā)展,海量數(shù)據(jù)傳輸與交換對系統(tǒng)帶寬的需求越來越高。傳統(tǒng)的并行總線帶寬已不能滿足當(dāng)前系統(tǒng)的需求,取而代之的是以PCIE為核心的第三代高速串行總線。PCIE總線采用點對點基于報文交換的數(shù)據(jù)傳輸方式,具有出色的電氣性能。同時,CPCI平臺因具有高開放性、高可靠性、可熱插拔、易于加固和低成本等優(yōu)勢而獲得廣泛應(yīng)用。但CPCI平臺采用PCI總線作為其數(shù)據(jù)傳輸通道,其傳輸帶寬的限制,嚴(yán)重阻礙了CPCI平臺在高速率、高帶寬領(lǐng)域的發(fā)展。 本文針對PCI總線帶寬的不足,將PCIE總線引入CPCI平臺,完成CPCI平臺下PCIE總線高速交換背板的研制。首先分析了CPCI平臺下PCIE信號互連引起的信號完整性、電源完整性、電磁兼容等關(guān)鍵問題。其次根據(jù)PCIE總線拓?fù)浣Y(jié)構(gòu)的特點,進(jìn)行了PCIE整體交換架構(gòu)和各功能模塊的詳細(xì)設(shè)計,完成了高速交換背板的PCB疊層、布局、布線,在設(shè)計中采用傳輸線理論+PCIE布線規(guī)范+EDA仿真相結(jié)合的方法,有效控制了PCIE信號在PCB板與高速連接器上傳輸時的信號完整性。最后通過對PCIE總線高速交換背板的性能指標(biāo)進(jìn)行測試,每一條PCIE數(shù)據(jù)鏈路可提供1.5Gbps的帶寬,背板整體交換能力達(dá)到7.5Gbps,驗證了方案的正確性與可行性。 本文將PCIE信號引入CPCI平臺,可解決CPCI平臺中差異化設(shè)備板卡接入時PCI總線與PCIE總線共存的問題。因背板具有大容量交換的性能,系統(tǒng)可用于電信設(shè)備、網(wǎng)絡(luò)通訊、工業(yè)控制、航空航天、軍事裝備等對設(shè)備機械性能和電氣性能要求較高的領(lǐng)域。同時也為其他高速串行總線引入CPCI平臺提供一定的參考。此外,對其他高速信號在CPCI背板中互連也有一定的參考價值。
[Abstract]:With the rapid development of microprocessor technology, multimedia technology and network technology, the demand of mass data transmission and exchange for system bandwidth is increasing. The traditional parallel bus bandwidth can no longer meet the needs of the current system. Instead, the third generation high-speed serial bus, .PCIE, which takes PCIE as the core, adopts a point-to-point data transmission mode based on message exchange, which has excellent electrical performance. At the same time, CPCI platform has been widely used because of its advantages of high openness, high reliability, hot pluggable, easy reinforcement and low cost. However, the CPCI platform uses PCI bus as its data transmission channel. The limitation of its transmission bandwidth seriously hinders the development of CPCI platform in the field of high speed and high bandwidth. Aiming at the shortage of PCI bus bandwidth, this paper introduces PCIE bus into CPCI platform, and completes the development of PCIE bus high speed switch backplane based on CPCI platform. Firstly, the signal integrity, power supply integrity and electromagnetic compatibility caused by PCIE signal interconnection on CPCI platform are analyzed. Secondly, according to the characteristics of PCIE bus topology, the PCIE switching architecture and each functional module are designed in detail, and the PCB stack, layout and wiring of the high-speed switching backplane are completed. In the design, the transmission line theory PCIE routing specification EDA simulation method is used to effectively control the signal integrity of PCIE signal transmitted on PCB board and high speed connector. Finally, by testing the performance index of PCIE bus high-speed switching backplane, each PCIE data link can provide the bandwidth of 1.5Gbps, and the overall switching capability of backplane reaches 7.5 Gbps. the correctness and feasibility of the scheme are verified. In this paper, the PCIE signal is introduced into the CPCI platform, which can solve the problem of the coexistence of PCI bus and PCIE bus when the differential device card is connected in the CPCI platform. Because the backplane has the capability of large capacity exchange, the system can be used in the fields of telecommunication equipment, network communication, industrial control, aerospace, military equipment and so on, which require higher mechanical and electrical performance of the equipment. At the same time, it also provides some reference for other high speed serial bus to introduce CPCI platform. In addition, it has some reference value for other high-speed signals interconnecting in CPCI backplane.
【學(xué)位授予單位】：北京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP336

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