本文選題：PCI + Express接口　； 參考：《控制工程》2017年08期

【摘要】：針對(duì)PCI Express接口的FPGA中基于HDL狀態(tài)機(jī)的傳統(tǒng)設(shè)計(jì)方法中效率低下和復(fù)雜度高等不足,探討一種SOPC中基于IP核的嵌入式設(shè)計(jì)方法,提出基于Xilinx最新Zynq平臺(tái)PCI Express接口設(shè)計(jì)方案。在Zynq芯片的PL部分實(shí)現(xiàn)PCI Express接口模塊、AXI-Stream和AXI的協(xié)議轉(zhuǎn)換以及動(dòng)態(tài)地址轉(zhuǎn)換,PS部分實(shí)現(xiàn)AXI數(shù)據(jù)接口和DDR3接口模塊,利用AXI互聯(lián)器實(shí)現(xiàn)PL和PS中主從設(shè)備的通信。通過運(yùn)行編寫的頂層測(cè)試文件得到仿真波形,以及利用邏輯診斷IP核捕捉測(cè)試程序運(yùn)行時(shí)的數(shù)據(jù)信號(hào),實(shí)現(xiàn)對(duì)接口設(shè)計(jì)的驗(yàn)證。在設(shè)計(jì)效率提升時(shí)降低其復(fù)雜度,具有集成度高、可移植性強(qiáng)和通用性好等特點(diǎn),為PCB IC芯片間、功能模塊背板總線或光纖設(shè)備傳輸中的數(shù)據(jù)通信接口提供了一種解決方案。
[Abstract]:Aiming at the low efficiency and high complexity of the traditional design method based on HDL state machine in FPGA with PCI Express interface, this paper discusses an embedded design method based on IP core in SOPC, and proposes a design scheme of PCI Express interface based on the latest Zynq platform of Xilinx. In the PL part of Zynq chip, the protocol translation between PCI Express interface module, AXI-Stream and AXI, and the dynamic address translation module, AXI data interface and DDR3 interface module are realized, and the communication between PL and PS main and slave devices is realized by AXI interconnecting device. The simulation waveform is obtained by running the top-level test file and the data signal of the test program is captured by using the logic diagnostic IP core to verify the design of the interface. With the advantages of high integration, high portability and good versatility, the design efficiency is reduced when the design efficiency is improved. It provides a solution for the data communication interface between PCB IC chips, the functional module backplane bus or the optical fiber device transmission.
【作者單位】： 中南大學(xué)信息科學(xué)與工程學(xué)院;
【基金】：國(guó)家863計(jì)劃項(xiàng)目“大規(guī)模PLC研發(fā)及應(yīng)用”(2013AA040301-3)
【分類號(hào)】：TP334.7
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本文編號(hào)：1872379