本文選題：串行接口 + 多通道緩沖串口�。� 參考：《東南大學》2016年碩士論文

【摘要】：近年來,隨著集成電路技術(shù)的迅猛發(fā)展,處理器和內(nèi)存性能的飛速提高,處理器內(nèi)部以及處理器之間的數(shù)據(jù)交互的頻率和交互的數(shù)據(jù)量也在高速增長,這就對數(shù)據(jù)傳輸?shù)男侍岢隽烁叩囊�。McBSP (Multichannel Buffered Serial Port,多通道緩沖串行接口)既可以實現(xiàn)時分多路串行通信功能,又可以通過DSP提供的DMA總線連接實現(xiàn)不通過CPU直接進行自動緩存功能,從而使得DSP能夠從繁重的串口通訊任務(wù)中解放出來,提高了DSP的整體運行速率。本論文主要以多通道緩沖串行接口為研究主題,深入分析了目前國內(nèi)外的發(fā)展趨勢,研究了SPI(Serial Peripheral Interface,串行外設(shè)接口)總線接口,中斷,μ律和A律壓縮的相關(guān)技術(shù),完成了多通道緩沖串行接口的設(shè)計。本文闡述了McBSP的整體功能、性能和結(jié)構(gòu),說明了McBSP的基本工作流程,詳細描述了McBSP每個功能模塊的具體設(shè)計。針對當使用McBSP壓擴芯片內(nèi)部數(shù)據(jù)時,CPU或DMA控制器無法監(jiān)控接收和發(fā)送中斷或同步事件的變化,若全程使用輪詢方式監(jiān)控這些變化則會影響數(shù)據(jù)的讀寫速率這一問題,增加數(shù)字環(huán)回模式(DLB)與非數(shù)字環(huán)回模式(非-DLB)的選擇。針對于有時同時進行多個數(shù)據(jù)單元的讀寫操作的需求,加入了多通道選擇模塊。在驗證方面,運用Xilinx的開發(fā)工具搭建測試平臺,呈現(xiàn)了平臺搭建的整個過程,對本設(shè)計的McBSP模塊系統(tǒng)進行了7種基本的測試,包括時鐘與幀同步配置驗證、中斷處理能力驗證、數(shù)據(jù)壓縮處理能力驗證、通道選擇驗證、幀同步忽略驗證、數(shù)據(jù)發(fā)送與接收驗證、SPI接口兼容性驗證,確保McBSP模塊功能的準確性。在Xilinx公司的Virtex7系列開發(fā)板上對設(shè)計進行驗證,驗證結(jié)果表明本文設(shè)計的McBSP串行接口支持串行數(shù)據(jù)讀寫操作,支持中斷操作,支持全雙工的數(shù)據(jù)傳輸模式,支持數(shù)據(jù)壓縮模式傳輸,支持多通道選擇,支持SPI協(xié)議,最高時鐘頻率可達到260.281MHz.經(jīng)過測試平臺的驗證,論文設(shè)計的McSBP模塊功能完善,性能可靠,己完全達到設(shè)計的功能和性能要求,可以在DSP片內(nèi)進行使用。
[Abstract]:In recent years, with the rapid development of integrated circuit technology and the rapid improvement of processor and memory performance, the frequency of data interaction and the amount of data between processors are also growing rapidly. This puts forward higher requirements for the efficiency of data transmission. McBSP / Multichannel Buffered Serial (multi-channel buffering serial interface) can realize the function of time-division and multi-channel serial communication. The DMA bus connection provided by DSP can also realize the function of automatic cache without CPU, thus DSP can be freed from the heavy serial communication task, and the overall running rate of DSP can be improved. In this paper, the multi-channel buffer serial interface is the main research topic, and the development trend at home and abroad is deeply analyzed, and the related technologies of SPI(Serial Peripheral interface, interrupt, 渭 law and A law compression are studied. The design of multi-channel buffer serial interface is completed. This paper describes the whole function, performance and structure of McBSP, explains the basic workflow of McBSP, and describes the design of each function module of McBSP in detail. In view of the fact that McBSP or DMA controller can not monitor the changes of receiving and sending interrupt or synchronous events when the internal data of McBSP is used, the rate of reading and writing of data will be affected if the changes are monitored by polling. The selection of digital loop mode (DLB) and non-digital loop mode (non--DLB) is added. To meet the need of reading and writing of multiple data units at the same time, a multi-channel selection module is added. In the aspect of verification, using the development tools of Xilinx to build the test platform, the whole process of the platform is presented. The McBSP module system designed in this paper has carried out seven basic tests, including clock and frame synchronization configuration verification, interrupt processing ability verification. Data compression processing capability verification, channel selection verification, frame synchronization ignoring verification, data sending and receiving verification and compatibility verification of SPI interface ensure the accuracy of McBSP module function. The design is verified on the Virtex7 series development board of Xilinx Company. The result shows that the McBSP serial interface designed in this paper supports serial data reading and writing operation, interrupt operation and full duplex data transmission mode. It supports data compression mode transmission, multi-channel selection and SPI protocol. The highest clock frequency can reach 260.281 MHz. After verification of the test platform, the McSBP module designed in this paper has perfect function and reliable performance, which can be used in DSP chip.
【學位授予單位】：東南大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TP334.7;TP332

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