本文選題：YHFT-Matrix + 外部存儲器接口��； 參考：《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：YHFT-Matrix處理器是國防科技大學(xué)設(shè)計的一款高性能DSP，主要面向3GPP-LTE無線通信基帶處理領(lǐng)域。采用VLIW結(jié)構(gòu)，16/32位可變長類RSIC指令集，每周期最大流出10條指令。處理器包含標量和向量兩部分運算單元，標量單元負責簡單的計算以及程序流控，向量單元內(nèi)含有多個向量運算部件，提供主要的運算能力。 現(xiàn)今運算能力的大幅提高對存儲器的數(shù)據(jù)傳輸速率有了更高的要求。為了設(shè)計出更高性能的外部存儲器接口（EMIF）部件，本文從研究DDR2存儲器的結(jié)構(gòu)和時序特點入手，并根據(jù)YHFT-Matrix處理器的體系結(jié)構(gòu)設(shè)計出一款能夠同時處理四核訪問請求的EMIF。同時兼顧DDR2SDRAM和ASRAM的結(jié)構(gòu)特點，，完成了適用于本款高性能DSP的EMIF設(shè)計、驗證與測試，DDR2SDRAM的連接與板級測試。 針對YHFT-Matrix處理器內(nèi)部數(shù)據(jù)通路結(jié)構(gòu)，提出了EMIF模塊對各請求源進行輪轉(zhuǎn)式仲裁、根據(jù)優(yōu)先級排序，并將通信協(xié)議轉(zhuǎn)換成AXI總線的協(xié)議的設(shè)計方法。最終使得12個請求源能夠公平的訪問外存。在協(xié)議轉(zhuǎn)換時，由于外部存儲器與內(nèi)核時鐘頻率不同，本文設(shè)計了一個異步對接，負責將500Mhz時鐘域下的內(nèi)核信號同步到DDR2SDRAM采用的200Mhz時鐘域。在完成驗證與測試之后，本文對EMIF的傳輸方式又做了部分修改，使得傳輸效率有了大幅提升。 采用了將DDR2控制器（固核）和PHY（硬核）集成到Y(jié)HFT-Matrix處理器內(nèi)的連接策略，并深入分析了YHFT-Matrix處理器中的DDR2接口。DDR2接口可以外接4個16-bit位寬的1Gbit器件組成4Gbit的DDR2存儲器。DDR2PHY的時鐘達200Mhz，數(shù)據(jù)寬度為64位。DDR2控制器對芯片內(nèi)部提供AXI數(shù)據(jù)總線和APB配置總線接口，并負責為指令Cache、數(shù)據(jù)Cache和DMA（直接存儲器訪問接口）提供程序和數(shù)據(jù)。DDR2SDRAM通過EMIF模塊與處理器內(nèi)核連接起來。 此外，本文對以上設(shè)計進行了較為系統(tǒng)地驗證，并進行了板級測試。測試結(jié)果表明，單核得到DDR2SDRAM讀每個字最短時間為15ns，寫一個字最短時間為10ns，四核同時讀的情況也可維持單核的15ns一個字。在優(yōu)化后，單核DMA讀速率有了接近50%的提高，但四核同時讀的速率并沒有顯著提高。
[Abstract]:YHFT-Matrix processor is a high performance DSP designed by the University of National Defense Science and Technology. It is mainly oriented to the baseband processing field of 3GPP-LTE wireless communication. A 16 / 32 bit variable length RSIC instruction set with VLIW structure is used, with a maximum outflow of 10 instructions per cycle. The processor consists of scalar unit and vector unit. Scalar unit is responsible for simple calculation and program flow control. Nowadays, the great improvement of computing power requires higher data transmission rate of memory. In order to design a higher performance external memory interface (EMIF) component, this paper studies the structure and timing characteristics of DDR2 memory, and designs an EMIF which can process four-core access requests simultaneously according to the architecture of YHFT-Matrix processor. At the same time, considering the structural characteristics of DDR2SDRAM and ASRAM, the design of EMIF suitable for this high performance DSP is completed, and the connection and board test of DDR2 SDRAM are verified and tested. Aiming at the internal data path structure of YHFT-Matrix processor, this paper presents a design method for EMIF module to rotate each request source, sort it according to priority, and convert the communication protocol to AXI bus. Finally, 12 request sources can access the external memory equitably. In the protocol conversion, because the external memory and the kernel clock frequency are different, this paper designs an asynchronous docking, which is responsible for synchronizing the kernel signals in the 500Mhz clock domain to the 200Mhz clock domain adopted by DDR2SDRAM. After completing the verification and testing, the transmission mode of EMIF is partly modified in this paper, which greatly improves the transmission efficiency. The connection strategy of integrating DDR2 controller (fixed core) and PHY (hard core) into YHFT-Matrix processor is adopted. The DDR2 interface. DDR2 interface in YHFT-Matrix processor can be connected with four 1Gbit devices with 16-bit width to form 4Gbit DDR2 memory. DDR2PHY clock is 200Mhz. the data width is 64 bits. DDR2 controller provides AXI data bus and APB configuration bus interface to the chip. It is also responsible for providing programs and data. DDR2 SDRAM for instruction Cache. data Cache and DMA (Direct memory access Interface). The SDRAM is connected to the processor kernel through the EMIF module. In addition, the above design is systematically verified and tested at board level. The test results show that the minimum time for DDR2SDRAM to read each word is 15ns, and the shortest time for writing a word is 10ns.The four-core simultaneous reading can also maintain a single core 15ns word. After optimization, the reading rate of mononuclear DMA was increased by nearly 50%, but the rate of simultaneous reading by four cores was not significantly increased.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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