本文選題：SRAM + 邏輯努力��； 參考：《華中科技大學(xué)》2012年碩士論文

【摘要】：SRAM（Static Random Access Memory）是SOC（System On Chip）中最為常見的模塊之一，隨著工藝的進(jìn)步，片上SRAM的速度和容量都取得了飛速的發(fā)展。大容量的SRAM勢必會帶來更多的功耗開銷，因而高速、大容量、低功耗SRAM的設(shè)計是當(dāng)今研究的熱點和難點。 本文結(jié)合實際應(yīng)用需求，，采用自底向上的層次化方法，設(shè)計了一個全定制8K×32b的SRAM。從SRAM最基本的存儲單元開始，依據(jù)當(dāng)前SRAM存儲單元存在的幾種方案，對比分析選定了適合本課題的6管存儲單元。同時，為了降低功耗，采用字線分割技術(shù)將存儲陣列劃分為4塊。采用了預(yù)譯碼和分塊譯碼技術(shù)設(shè)計SRAM的譯碼電路可以提高譯碼速度并降低面積開銷；門控時鐘技術(shù)可以進(jìn)一步降低系統(tǒng)功耗；精心設(shè)計的預(yù)充電路可以減小預(yù)充電的等待時間。最后為了精確控制靈敏放大器的開啟時間，降低工藝和外界因素對其的影響，避免位線放電過多，本文采用改進(jìn)的replica bitline結(jié)構(gòu)來控制靈敏放大器的使能信號，因而可以較為準(zhǔn)確的控制位線放電，使位線放電到100mV左右的電壓差時開啟靈敏放大器。 本文設(shè)計的256Kb SRAM電路采用SMIC0.18m CMOS工藝在Cadence Virtuso平臺下完成全定制設(shè)計，并采用Nanosim對SRAM整體電路進(jìn)行仿真驗證。和Memory Complier自動生成的SRAM相比，在TT工藝角下，本文設(shè)計的SRAM讀取延時為2.095ns，比前者快0.5ns左右；平均功耗為10.53mW，約為前者的八分之一。因此本文設(shè)計的SRAM非常適合應(yīng)用于低功耗、高速SOC中。 本文獨創(chuàng)性的工作包括：采用邏輯努力方法設(shè)計了一種高速譯碼電路；分析指出傳統(tǒng)replica bitline結(jié)構(gòu)可能存在反饋震蕩的問題，并通過仿真證實了這些問題的存在；結(jié)合replica bitline結(jié)構(gòu)提出了一種改進(jìn)的replica bitline結(jié)構(gòu)來解決傳統(tǒng)replicabitline結(jié)構(gòu)存在的問題，并仿真驗證了改進(jìn)的replica bitline電路；采用字線分割技術(shù)和分塊技術(shù)將存儲陣列分為4塊，不僅降低了字線負(fù)載電容、加快讀取速度，而且分塊結(jié)構(gòu)可以只激活選中的存儲塊，這樣可以大大降低存儲器的功耗。
[Abstract]:SRAM(Static Random Access memory is one of the most common modules in SOC(System on chip. With the development of technology, the speed and capacity of SRAM on chip have been developed rapidly. Large capacity SRAM is bound to bring more power consumption overhead, so the design of high speed, large capacity and low power SRAM is a hot and difficult point. In this paper, a fully customizable 8K 脳 32b SRAM is designed by using the bottom-up hierarchical method combined with the practical application requirements. Starting from the most basic memory cell of SRAM, according to several schemes of current SRAM storage cell, the 6 tube memory cells suitable for this subject are selected by comparison and analysis. At the same time, in order to reduce power consumption, the memory array is divided into 4 blocks using word line segmentation technology. Using predecoding and block decoding techniques to design the decoding circuit of SRAM can improve the decoding speed and reduce the area overhead; the gating clock technology can further reduce the power consumption of the system; and the carefully designed precharging circuit can reduce the waiting time of precharging. Finally, in order to accurately control the opening time of the sensitive amplifier, reduce the influence of process and external factors on it, and avoid excessive bit line discharge, an improved replica bitline structure is used to control the enabling signal of the sensitive amplifier. Thus, the bit line discharge can be controlled accurately, and the sensitive amplifier can be turned on when the bit line discharge to the voltage difference about 100mV. The 256Kb SRAM circuit designed in this paper uses SMIC0.18m CMOS process to complete the full customization design under the Cadence Virtuso platform, and Nanosim is used to simulate the whole SRAM circuit. Compared with SRAM generated automatically by Memory Complier, the read delay of SRAM designed in this paper is 2.095ns, which is faster than that of SRAM generated automatically by Memory Complier, and the average power consumption is 10.53mW, which is about 1/8 of the former. Therefore, the SRAM designed in this paper is very suitable for low power consumption and high speed SOC. The original work of this paper includes: designing a high speed decoding circuit by using logical effort method, analyzing and pointing out that the traditional replica bitline structure may have the problem of feedback oscillation, and validating the existence of these problems by simulation. Combined with replica bitline structure, an improved replica bitline structure is proposed to solve the problems existing in traditional replicabitline structure, and the improved replica bitline circuit is verified by simulation, and the memory array is divided into 4 blocks by word line segmentation and block dividing technology. Not only the load capacitance of the word line is reduced and the read speed is accelerated, but also the block structure can only activate the selected memory block, which can greatly reduce the memory power consumption.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TN47;TP368.1

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前2條

1 呂韜;高速低功耗嵌入式SRAM的設(shè)計與優(yōu)化[D];國防科學(xué)技術(shù)大學(xué);2009年

2 趙堯;流水線圖像旋轉(zhuǎn)ASIC設(shè)計與實現(xiàn)[D];華中科技大學(xué);2009年

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