本文選題：量子計(jì)算機(jī) + 三值量子系統(tǒng)�。� 參考：《東華大學(xué)》2017年碩士論文

【摘要】：量子邏輯系統(tǒng)分為二值量子系統(tǒng)和多值量子系統(tǒng),目前對多值量子系統(tǒng)的研究甚少,但多值量子系統(tǒng)在信息安全、編碼量子位等方面都優(yōu)于二值量子系統(tǒng),所以未來往多值量子系統(tǒng)發(fā)展是一種趨勢。三值量子系統(tǒng)作為多值量子系統(tǒng)的最小情況,具有重要的研究意義,從已有的三值量子邏輯電路的研究成果中可以發(fā)現(xiàn),研究者對于三值量子邏輯電路的研究大多側(cè)重于綜合方法,而對其優(yōu)化方法的研究較少,因此,本文對三值量子邏輯電路的優(yōu)化設(shè)計(jì)進(jìn)行了研究,具體研究內(nèi)容如下:(1)提出并證明了14條三值量子邏輯電路優(yōu)化規(guī)則。根據(jù)三值量子基本門級聯(lián)的特性,總結(jié)出14條優(yōu)化規(guī)則,這些優(yōu)化規(guī)則適用于大多數(shù)三值量子邏輯電路,可以有效的優(yōu)化由三值Toffoli門、三值Feynman門、三值M-S門構(gòu)成的三值量子邏輯電路。(2)設(shè)計(jì)出了三值量子邏輯電路優(yōu)化算法�；谏鲜龅�14條優(yōu)化規(guī)則,設(shè)計(jì)出了三值量子邏輯電路優(yōu)化算法,然后使用C語言在VC++6.0環(huán)境下對該算法進(jìn)行了編程實(shí)現(xiàn),以便當(dāng)三值量子邏輯電路的輸入位數(shù)和門數(shù)過多時(shí),仍能參照本文設(shè)計(jì)的14條優(yōu)化規(guī)則去優(yōu)化電路。(3)實(shí)現(xiàn)了三值量子全加器、全減器、加減器的優(yōu)化設(shè)計(jì)。依次對n位三值量子全加器、全減器、加減器進(jìn)行了人工設(shè)計(jì),再使用上述的優(yōu)化算法對電路進(jìn)行改良,改良后的電路與目前已見報(bào)道的同類型電路相比,量子代價(jià)和輔助線都是最少的,是當(dāng)前該類型電路的最優(yōu)設(shè)計(jì),對三值量子邏輯電路的設(shè)計(jì)有啟發(fā)作用,也進(jìn)一步證明了本文設(shè)計(jì)的優(yōu)化規(guī)則及優(yōu)化算法的實(shí)用性。(4)實(shí)現(xiàn)了三值量子乘法器的優(yōu)化設(shè)計(jì)。目前尚未見到有使用三值Toffoli門、三值Feynman門及三值M-S門設(shè)計(jì)的三值量子乘法器的報(bào)道,因此,本文設(shè)計(jì)出了一位三值量子乘法器的電路并利用上述優(yōu)化算法對電路進(jìn)行改進(jìn),最后基于常規(guī)邏輯的陣列乘法器組成原理設(shè)計(jì)出了n×n位三值量子乘法器,為三值量子邏輯電路的設(shè)計(jì)提供參考。
[Abstract]:Quantum logic system is divided into binary quantum system and multivalued quantum system. At present, there is little research on multivalued quantum system, but multivalued quantum system is superior to binary quantum system in information security, coding quantum bit and so on. Therefore, the future development of multivalued quantum systems is a trend. Ternary quantum systems, as the minimum case of multivalued quantum systems, are of great significance in the study of ternary quantum logic circuits. Most of the researches on ternary quantum logic circuits are focused on synthesis methods, but few on their optimization methods. Therefore, the optimization design of ternary quantum logic circuits is studied in this paper. The main contents of this paper are as follows: (1) the optimization rules of 14 ternary quantum logic circuits are proposed and proved. According to the characteristics of ternary quantum basic gate cascade, 14 optimization rules are summarized. These optimization rules are suitable for most ternary quantum logic circuits, and can be effectively optimized by ternary Toffoli gate and ternary Feynman gate. The ternary quantum logic circuit composed of ternary M-S gate is designed and the optimization algorithm of ternary quantum logic circuit is designed. Based on the above 14 optimization rules, a ternary quantum logic circuit optimization algorithm is designed, and the algorithm is programmed in VC 6.0. When the number of input bits and gates of ternary quantum logic circuits is too many, the optimal design of ternary quantum total adder, total subtracter and subtractor can still be realized by referring to the 14 optimization rules designed in this paper. The n-bit ternary quantum total adder, full subtracter and subtractor are designed manually, and then the circuit is improved by using the above optimization algorithm. The improved circuit is compared with the same type of circuit that has been reported at present. The quantum cost and auxiliary line are the least, which is the optimal design of the current type of circuit, which is instructive to the design of ternary quantum logic circuit. It is further proved that the optimization rules and the practicability of the optimization algorithm are used to realize the optimal design of the ternary quantum multiplier. There are no reports of ternary quantum multiplier designed by ternary Toffoli gate, ternary Feynman gate and ternary M-S gate. Therefore, a ternary quantum multiplier circuit is designed and improved by using the above optimization algorithm. Finally, an n 脳 n bit ternary quantum multiplier is designed based on the principle of array multiplier of conventional logic, which provides a reference for the design of ternary quantum logic circuit.
【學(xué)位授予單位】：東華大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP331;O413

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