本文選題：寄存器文件 + 全定制��； 參考：《哈爾濱工業(yè)大學(xué)》2012年碩士論文

【摘要】：寄存器文件位于處理器內(nèi)核中，且一般處于數(shù)據(jù)通路上，其性能的好壞直接關(guān)系到處理器的性能。尤其在一些關(guān)鍵應(yīng)用場(chǎng)合對(duì)處理器的性能指標(biāo)要求非常高，這就需要設(shè)計(jì)在面積、速度、功耗幾個(gè)方面達(dá)到最優(yōu)化的寄存器文件。 本文的寄存器文件要應(yīng)用在一款高性能DSP處理器上，根據(jù)處理器的結(jié)構(gòu)確定了相應(yīng)的設(shè)計(jì)要求，研究了多端口寄存器文件的全定制設(shè)計(jì)和實(shí)現(xiàn)技術(shù)，并采用了全定制的方法對(duì)其進(jìn)行設(shè)計(jì)。 在傳統(tǒng)6管存儲(chǔ)單元的基礎(chǔ)上，對(duì)其進(jìn)行修改，，添加了讀寫端口，消除了讀破壞，并基于統(tǒng)計(jì)學(xué)的基礎(chǔ)上，做出了反相讀出的設(shè)計(jì)，減小了功耗的同時(shí)加快了讀出數(shù)據(jù)的速度。對(duì)譯碼器的設(shè)計(jì)在分析了靜態(tài)邏輯與動(dòng)態(tài)邏輯的基礎(chǔ)上決定采用兩級(jí)動(dòng)態(tài)譯碼，在速度與穩(wěn)定性兩者之間取得了很好的平衡。設(shè)計(jì)定向通路，這一電路結(jié)構(gòu)的存在進(jìn)一步優(yōu)化了讀操作。 本文對(duì)版圖設(shè)計(jì)的過程和一般技術(shù)進(jìn)行了研究，在進(jìn)行版圖設(shè)計(jì)時(shí)，分別采用了手指狀折疊技術(shù)、電源地共享、源漏共用等一系列技術(shù)減少了19%的版圖面積。 本文還對(duì)寄存器文件時(shí)序庫(kù)的建立進(jìn)行了研究和實(shí)現(xiàn)，為以后單元庫(kù)的建立打下了良好的基礎(chǔ)。采用Synopsys的Liberty NCX建庫(kù)工具對(duì)設(shè)計(jì)進(jìn)行了時(shí)序庫(kù)的建立，在這過程當(dāng)中介紹了時(shí)序信息的提取、時(shí)序弧的測(cè)量、采樣點(diǎn)的選擇等與建庫(kù)緊密相關(guān)的知識(shí)。 本文在65nm工藝下完成了一個(gè)具有10個(gè)讀端口6個(gè)寫端口，容量為32×32位、能夠在單周期內(nèi)完成數(shù)據(jù)寫入并讀出、含有定向通路的寄存器文件。該寄存器文件頻率可以達(dá)到600MHz。
[Abstract]:The register file is located in the processor kernel and generally in the data path, and its performance is directly related to the processor performance. Especially in some key applications, the performance requirements of the processor are very high, which requires the design of the optimal register file in area, speed and power consumption. The register file in this paper should be applied to a high-performance DSP processor. According to the structure of the processor, the corresponding design requirements are determined, and the full customization design and implementation technology of the multi-port register file is studied. The method of full customization is used to design it. On the basis of the traditional 6-transistor memory cell, we modify it, add the read and write port, eliminate the reading damage, and based on statistics, we make the design of inverse readout, which reduces the power consumption and speeds up the readout speed. The design of the decoder is based on the analysis of static logic and dynamic logic, and it is decided to adopt two-stage dynamic decoding, which achieves a good balance between speed and stability. By designing the directional path, the existence of this circuit structure further optimizes the read operation. In this paper, the process and general technology of layout design are studied. In the process of layout design, a series of techniques, such as finger folding, power sharing and source-drain sharing, are used to reduce the layout area by 19%. In this paper, the establishment of register file timing library is also studied and implemented, which lays a good foundation for the establishment of unit library in the future. In this paper, the time sequence database is built by using the Liberty NCX database tool of Synopsys. In the process, the extraction of time sequence information, the measurement of sequential arc, the selection of sampling points and so on are introduced, which are closely related to the construction of the database. In this paper, a register file with 10 read ports and 6 write ports, with capacity of 32 脳 32 bits, can be written and read out in a single cycle under 65nm technology. The frequency of the register file can reach 600 MHz.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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