本文選題：并行計(jì)算機(jī) + 互連網(wǎng)絡(luò)��； 參考：《計(jì)算機(jī)研究與發(fā)展》2016年02期

【摘要】：當(dāng)前在大規(guī)模并行計(jì)算機(jī)中,多數(shù)并行程序的用戶習(xí)慣于使用虛擬地址進(jìn)行編程.因此,虛擬地址與物理地址之間的轉(zhuǎn)換效率直接影響了并行程序的執(zhí)行性能,而cache能夠有效地提高虛實(shí)地址轉(zhuǎn)換的效率并降低延遲.提出了一種在大規(guī)模并行計(jì)算機(jī)互連網(wǎng)絡(luò)中的地址轉(zhuǎn)換cache.它采用了嵌入式DRAM(embedded dynamic random access memory,eDRAM)存儲(chǔ)器,容納更多的地址轉(zhuǎn)換表項(xiàng),從而提高命中率.并設(shè)計(jì)一種eDRAM刷新機(jī)制,隱藏了刷新操作,避免刷新導(dǎo)致的性能損失.ATC(address translation cache)中實(shí)現(xiàn)了諸如糾錯(cuò)碼與旁路機(jī)制等多種可靠性設(shè)計(jì).在32個(gè)計(jì)算結(jié)點(diǎn)上運(yùn)行業(yè)界公認(rèn)的NPB測(cè)試程序,結(jié)果顯示32個(gè)結(jié)點(diǎn)中ATC的平均命中率達(dá)到了95.3%,表明ATC設(shè)計(jì)的正確性與高性能.并且通過(guò)與3種傳統(tǒng)SRAM(static random access memory)實(shí)現(xiàn)的cache進(jìn)行對(duì)比實(shí)驗(yàn),說(shuō)明了cache容量是提高命中率的關(guān)鍵因素.
[Abstract]:At present, in large-scale parallel computers, most users of parallel programs are accustomed to using virtual addresses for programming. Therefore, the efficiency of translation between virtual address and physical address directly affects the execution performance of parallel programs, while cache can effectively improve the efficiency of virtual and real address translation and reduce the delay. In this paper, an address translation cachein large scale parallel computer interconnection network is proposed. It uses embedded DRAM(embedded dynamic random access memory memory DRAM memory to accommodate more address translation table items, thus improving hit rate. A eDRAM refresh mechanism is designed, which hides the refresh operation and avoids the performance loss caused by the refresh. ATCU address translation cache) implements a variety of reliability designs such as error-correcting code and bypass mechanism. Running the recognized NPB test program on 32 computing nodes, the results show that the average hit rate of ATC in 32 nodes is up to 95.3, which indicates the correctness and high performance of ATC design. By comparing with three kinds of cache realized by traditional SRAM(static random access memory, it is proved that cache capacity is the key factor to improve hit rate.
【作者單位】： 國(guó)防科學(xué)技術(shù)大學(xué)計(jì)算機(jī)學(xué)院;
【基金】：國(guó)家自然科學(xué)基金項(xiàng)目(61103083,61133007) 國(guó)家“八六三”高技術(shù)研究發(fā)展計(jì)劃基金項(xiàng)目(2012AA01A301) 國(guó)家“九七三”重點(diǎn)基礎(chǔ)研究發(fā)展計(jì)劃基金項(xiàng)目(2011CB309705)~~
【分類號(hào)】：TP333

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