本文選題：高可靠性 + 星載計(jì)算機(jī)　； 參考：《南京理工大學(xué)》2013年碩士論文

【摘要】：空間技術(shù)的發(fā)展是國家科技水平和綜合國力的重要體現(xiàn),對(duì)國家的經(jīng)濟(jì)、國防和軍事建設(shè)有著重大影響。隨著我國空間探索腳步的不斷前進(jìn),宇航任務(wù)對(duì)星載計(jì)算機(jī)提出了更高的要求�？臻g環(huán)境的惡劣條件,對(duì)星載電子產(chǎn)品的性能、可靠性、壽命提出了嚴(yán)重的挑戰(zhàn),亟需研發(fā)出適應(yīng)未來空間飛行任務(wù)需要的高性能、高可靠的星載計(jì)算機(jī)。 本文以航天器高級(jí)電子系統(tǒng)技術(shù)研究項(xiàng)目為背景,研究符合高級(jí)電子系統(tǒng)規(guī)范的星載容錯(cuò)計(jì)算機(jī)體系結(jié)構(gòu),針對(duì)性的提出多處理器模塊并行冗余工作的計(jì)算機(jī)系統(tǒng)架構(gòu)。在此基礎(chǔ)上,研究基于高速串行數(shù)據(jù)傳輸實(shí)現(xiàn)的重定向系統(tǒng),實(shí)現(xiàn)處理器與接口電路的切換互連以及多個(gè)處理器之間的數(shù)據(jù)交互設(shè)計(jì),研究串行傳輸?shù)臅r(shí)鐘同步系統(tǒng)實(shí)現(xiàn)方法。根據(jù)任務(wù)特點(diǎn),提出了在子計(jì)算單元故障或者數(shù)據(jù)傳輸通道故障情況下的系統(tǒng)重構(gòu)策略。在完成架構(gòu)設(shè)計(jì)和重定向系統(tǒng)研究的基礎(chǔ)上,詳細(xì)闡述了星載容錯(cuò)計(jì)算機(jī)的電路設(shè)計(jì)。 文中對(duì)基于重定向互連的串行傳輸延時(shí)進(jìn)行分析計(jì)算,完成了同步時(shí)鐘系統(tǒng)的相位校準(zhǔn)測試和信號(hào)電氣特性測試,已驗(yàn)證設(shè)計(jì)方法和電路實(shí)現(xiàn)的正確性。
[Abstract]:The development of space technology is an important embodiment of national science and technology level and comprehensive national strength, and has a great influence on the national economy, national defense and military construction. With the continuous progress of space exploration in our country, the space mission has put forward higher requirements to the spaceborne computer. The bad conditions of space environment pose a serious challenge to the performance, reliability and lifetime of spaceborne electronic products. It is urgent to develop a high performance and reliable spaceborne computer to meet the needs of future space missions. In this paper, based on the research project of spacecraft advanced electronic system technology, the architecture of onboard fault-tolerant computer, which conforms to the specification of advanced electronic system, is studied, and a multi-processor module parallel redundant computer system architecture is proposed. On this basis, the redirect system based on high speed serial data transmission is studied, which realizes the switch and interconnection between processor and interface circuit and the design of data interaction between several processors. The realization method of clock synchronization system for serial transmission is studied. According to the characteristics of the task, the system reconstruction strategy in the case of sub-computing unit failure or data transmission channel failure is proposed. Based on the research of architecture design and redirection system, the circuit design of onboard fault-tolerant computer is described in detail. In this paper, the serial transmission delay based on redirect interconnection is analyzed and calculated, and the phase calibration test and the signal electrical characteristic test of the synchronous clock system are completed. The correctness of the design method and the circuit implementation is verified.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP303;V446

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 趙丹;徐國棟;劉源;;可重構(gòu)技術(shù)的航天應(yīng)用與星載計(jì)算機(jī)設(shè)計(jì)[J];哈爾濱工程大學(xué)學(xué)報(bào);2009年05期

2 米國偉;周海芳;杜云飛;;面向星載計(jì)算機(jī)的容錯(cuò)并行算法設(shè)計(jì)與實(shí)現(xiàn)[J];航空兵器;2010年04期

3 王九龍;;衛(wèi)星綜合電子系統(tǒng)現(xiàn)狀和發(fā)展建議[J];航天器工程;2007年05期

4 周定江;金明河;任偉;禹超;;基于LEON3的中央控制器設(shè)計(jì)及EDAC功能實(shí)現(xiàn)[J];機(jī)械與電子;2011年10期

5 鐘義信;;人工智能的突破與科學(xué)方法的創(chuàng)新[J];模式識(shí)別與人工智能;2012年03期

6 汪東升,鄭緯民,楊孝宗,王春露;TMR計(jì)算機(jī)系統(tǒng)FT-HIT的冗余管理技術(shù)[J];計(jì)算機(jī)工程與設(shè)計(jì);1997年02期

7 楊翠虹;文豐;姚宗;;基于LVDS的高速數(shù)據(jù)傳輸系統(tǒng)的設(shè)計(jì)[J];通信技術(shù);2010年09期

8 趙明富;嵌入式系統(tǒng)的總線技術(shù)及其應(yīng)用[J];微計(jì)算機(jī)信息;2005年07期

9 閆景富;李淑秋;;LVDS和CML電平在高速串行連接中的應(yīng)用[J];微計(jì)算機(jī)應(yīng)用;2008年08期

10 趙增輝;劉中友;彭圻平;;高速差分信號(hào)的互連設(shè)計(jì)[J];無線電通信技術(shù);2010年01期

，

本文編號(hào)：1837554