本文選題：協(xié)議適應(yīng)層 + MicroBlaze��； 參考：《天津大學(xué)》2012年碩士論文

【摘要】：在計算機(jī)和工業(yè)系統(tǒng)中，設(shè)備之間經(jīng)常需要進(jìn)行高速的數(shù)據(jù)交換，隨著數(shù)據(jù)傳輸速率的提高，設(shè)備之間進(jìn)行數(shù)據(jù)傳輸存在的最大的問題是數(shù)據(jù)按照某種協(xié)議進(jìn)行傳輸后造成時鐘不同步，進(jìn)而導(dǎo)致數(shù)據(jù)的丟失，當(dāng)傳輸速率達(dá)到Gbps時這一問題更加嚴(yán)重。解決這一問題的關(guān)鍵技術(shù)是在設(shè)備間添加一個可以硬件實現(xiàn)的協(xié)議適應(yīng)層。 協(xié)議適應(yīng)層（Protocol Adaptation Layers，PAL）是WiGig聯(lián)盟定義的、在60GHz頻段上支持特定數(shù)據(jù)和顯示的協(xié)議標(biāo)準(zhǔn)。PAL不僅支持音視頻接口，如HDMI和DisplayPort，還支持通用I/O，如USB和PCIe，并且允許這些標(biāo)準(zhǔn)的接口以無線傳輸?shù)姆绞街苯釉L問Mac層和物理層。相比于其他通過軟件實現(xiàn)的協(xié)議，PAL可以在硬件中開發(fā)和實現(xiàn)，從而可以最大化的提高性能和降低功耗。 從WiGig的定義上看，PAL既支持PCIe接口，也提供對USB3.0接口的支持，，但是目前Xilinx公司所提供的FPGA開發(fā)板尚未提供對USB3.0的支持，因此，本文針對PCIe接口的PAL進(jìn)行了設(shè)計和開發(fā)。本文基于Xilinx Virtex-6FPGA搭建PCIe接口的PAL硬件平臺，PC端驅(qū)動將數(shù)據(jù)通過PCIe接口傳輸?shù)紽PGA上，MicroBlaze軟核處理器調(diào)用AXI4總線對數(shù)據(jù)進(jìn)行接收和處理，處理后的數(shù)據(jù)經(jīng)過GTX高速收發(fā)器傳輸?shù)较乱患塅PGA中。經(jīng)過規(guī)范化CSP語言對整個系統(tǒng)模型的驗證和優(yōu)化后，本文所搭建的PAL平臺在Xilinx ML605開發(fā)板上進(jìn)行了測試，PC端傳輸數(shù)據(jù)到FPGA上的速度可達(dá)6.4Gbps，F(xiàn)PGA之間數(shù)據(jù)的傳輸速度可達(dá)3.2Gbps。
[Abstract]:In computer and industrial systems, high speed data exchange is often needed between devices. With the increase of data transmission rate, the biggest problem of data transmission between devices is that the data is not synchronized after a certain protocol is transmitted, which leads to the loss of data, which is when the transmission rate reaches Gbps. The problem is even more serious. The key technology to solve this problem is to add a protocol adaptation layer that can be implemented by hardware between devices.
The Protocol Adaptation Layers (PAL) is defined by the WiGig alliance. The protocol standard.PAL that supports specific data and display on the 60GHz band not only supports audio and video interfaces, such as HDMI and DisplayPort, but also supports general I/O, such as USB and PCIe, and allows these standard interfaces to access the layers and objects directly in a wireless transmission. Compared with other protocols implemented by software, PAL can be developed and implemented in hardware, thus maximizing performance and reducing power consumption.
From the definition of WiGig, PAL not only supports the PCIe interface, but also provides support to the USB3.0 interface, but the FPGA development board provided by Xilinx has not yet provided the support for USB3.0. Therefore, this paper has designed and developed the PAL for the PCIe interface. This paper is based on Xilinx Virtex-6FPGA to build the hardware platform of the PCIe interface. The data is transmitted to FPGA through the PCIe interface, and the MicroBlaze soft core processor calls the AXI4 bus to receive and process the data. The processed data is transmitted to the next level FPGA through the GTX high-speed transceiver. After the verification and optimization of the whole system model by the standardized CSP language, the PAL platform built in this paper is developed in Xilinx ML605. The test on board shows that the speed of transmitting data from PC terminal to FPGA can reach 6.4Gbps, and the speed of data transmission between FPGA can reach 3.2Gbps..

【學(xué)位授予單位】：天津大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP334.7

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本文編號：1782857