本文選題：低功耗 + Cache��； 參考：《湖南大學(xué)》2012年碩士論文

【摘要】：隨著集成電路進(jìn)入深亞微米和納米級工藝階段，嵌入式微處理器系統(tǒng)的功耗問題已經(jīng)成為制約新一代微處理器系統(tǒng)發(fā)展最主要的因素之一。Cache技術(shù)是基于程序的局部性原理，為緩解主存與處理器的速度不匹配而引入的，是優(yōu)化計算機(jī)系統(tǒng)性能的關(guān)鍵技術(shù)。同時，Cache的功耗也占到了整個嵌入式微處理器系統(tǒng)功耗的一半左右。因此，設(shè)計高性能、低功耗的Cache結(jié)構(gòu)對提高整個嵌入式系統(tǒng)性能和降低系統(tǒng)功耗有著重大的意義。 可重構(gòu)技術(shù)是目前備受關(guān)注的一種Cache低功耗技術(shù)。它基于資源合理分配原則，使Cache具有可變的配置參數(shù)集，并根據(jù)應(yīng)用程序?qū)Y源的需求情況配置Cache結(jié)構(gòu)，使Cache資源得到有效的利用。建立在可重構(gòu)技術(shù)之上的自適應(yīng)Cache重構(gòu)算法能夠動態(tài)統(tǒng)計Cache的行為和性能信息并根據(jù)這些信息在程序運行時動態(tài)地改變Cache的配置，進(jìn)而在保證性能的前提下，有效地降低Cache功耗。本文針對嵌入式系統(tǒng)環(huán)境，提出了兩種自適應(yīng)Cache重構(gòu)算法。這兩種算法都利用狀態(tài)機(jī)在程序運行過程中動態(tài)分析程序的局部性特征，根據(jù)程序變化，動態(tài)配置Cache的容量和相聯(lián)度。 第一種算法是利用程序跳轉(zhuǎn)頻率作為程序特征的監(jiān)測參數(shù)，，以此判斷重構(gòu)時機(jī)，然后根據(jù)Cache訪問缺失率情況，運用優(yōu)化的結(jié)構(gòu)搜索方法在最短時間內(nèi)找到該段程序最合適的匹配結(jié)構(gòu)。這種算法比第二種算法更容易實現(xiàn)。經(jīng)實驗仿真發(fā)現(xiàn)，相比傳統(tǒng)固定Cache結(jié)構(gòu)，該方案可以平均降低約39%的功耗。 第二種算法改進(jìn)了第一種算法，摒棄了第一種算法中采用程序跳轉(zhuǎn)率作為衡量程序特征是否變化的參數(shù)，加入了程序工作集的思想，通過分析指令工作集簽名來判斷程序段是否發(fā)生了變化，這使程序段的特征變化監(jiān)測更加精確，有效減少了冗余重構(gòu)和錯失重構(gòu)的次數(shù)。實驗仿真發(fā)現(xiàn)，相比傳統(tǒng)固定Cache結(jié)構(gòu)，該方案可以平均降低約64%的功耗，最大可降低68%。同樣地，該算法最大能減小96%的Cache缺失率并能減少3%的應(yīng)用程序運行時鐘周期數(shù)。
[Abstract]:As integrated circuits enter deep submicron and nanoscale processes, the power consumption of embedded microprocessor systems has become one of the most important factors restricting the development of new generation microprocessor systems. Cache technology is based on the principle of program locality. In order to mitigate the mismatch between main memory and processor speed, it is a key technology to optimize the performance of computer system. At the same time, the power consumption of Cache accounts for about half of the power consumption of the embedded microprocessor system. Therefore, it is of great significance to design a high performance, low power Cache architecture to improve the performance of the whole embedded system and reduce the power consumption of the system. Reconfigurable technology is a kind of low power Cache technology. Based on the principle of rational resource allocation, Cache has a variable set of configuration parameters, and the Cache structure is configured according to the requirements of the application program, so that the Cache resources can be utilized effectively. The adaptive Cache refactoring algorithm based on reconfigurable technology can dynamically statistics the behavior and performance information of Cache and dynamically change the configuration of Cache while the program is running according to these information. The power consumption of Cache is reduced effectively. In this paper, two adaptive Cache reconstruction algorithms are proposed for embedded system environment. Both algorithms use the state machine to dynamically analyze the local characteristics of the program and dynamically configure the capacity and the degree of association of the Cache according to the program changes. In the first algorithm, the program jump frequency is used as the monitoring parameter of the program feature to judge the time of reconstruction, and then according to the Cache access loss rate, The optimal structure search method is used to find the most suitable matching structure in the shortest time. This algorithm is easier to implement than the second one. The experimental results show that the proposed scheme can reduce the power consumption by about 39% compared with the traditional fixed Cache structure. The second algorithm improved the first algorithm, abandoned the first algorithm to use the program jump rate as a parameter to measure the change of program characteristics, and added the idea of program working set. By analyzing the signature of the working set of instructions to determine whether the program segment has changed or not, it makes the feature change monitoring of the program segment more accurate, and effectively reduces the number of redundant and missed reconfiguration. The experimental results show that compared with the conventional fixed Cache architecture, the proposed scheme can reduce the power consumption by about 64% on average and reduce the maximum power consumption by 68%. Similarly, the algorithm can reduce the Cache deletion rate by 96% and the application clock cycle by 3%.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

【參考文獻(xiàn)】

相關(guān)期刊論文 前9條

1 鄭偉,姚慶棟,張明,劉鵬,張子男,周莉,李東曉;一種低功耗Cache設(shè)計技術(shù)的研究[J];電路與系統(tǒng)學(xué)報;2004年05期

2 張宇弘,王界兵,嚴(yán)曉浪,汪樂宇;標(biāo)志預(yù)訪問和組選擇歷史相結(jié)合的低功耗指令cache[J];電子學(xué)報;2004年08期

3 趙學(xué)梅,葉以正,李曉明,時銳;一種低功耗高性能的滑動Cache方案[J];計算機(jī)研究與發(fā)展;2004年11期

4 黃海林;范東睿;許彤;唐志敏;;嵌入式處理器中訪存部件的低功耗設(shè)計研究[J];計算機(jī)學(xué)報;2006年05期

5 劉彬;彭蔓蔓;;低功耗高性能的分離比較cache方案[J];計算機(jī)應(yīng)用研究;2007年10期

6 趙歡;蘇小昆;李仁發(fā);;一種低功耗動態(tài)可重構(gòu)cache方案[J];計算機(jī)應(yīng)用;2009年05期

7 魯欣,付宇卓;基于WDC結(jié)構(gòu)的低靜態(tài)功耗Cache設(shè)計[J];上海交通大學(xué)學(xué)報;2005年04期

8 陳章龍;嵌入式處理器的Cache結(jié)構(gòu)研究[J];小型微型計算機(jī)系統(tǒng);2004年07期

9 張宇弘,王界兵,嚴(yán)曉浪,汪樂宇;利用基地址相關(guān)的低功耗數(shù)據(jù)cache設(shè)計[J];浙江大學(xué)學(xué)報(工學(xué)版);2005年10期

本文編號：1777060