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基于閃存的高速PCIe固態(tài)存儲卡的研究與實(shí)現(xiàn)

發(fā)布時(shí)間:2018-04-17 12:03

  本文選題:閃存 + 多通道 ; 參考:《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文


【摘要】:隨著網(wǎng)絡(luò)、計(jì)算、存儲等技術(shù)的飛速發(fā)展,當(dāng)今世界逐漸變成了網(wǎng)絡(luò)的世界,數(shù)據(jù)的世界。以海量數(shù)據(jù)為基礎(chǔ)的數(shù)據(jù)密集型計(jì)算應(yīng)用的廣泛出現(xiàn),除了對存儲規(guī)模的龐大需求以外,對性能、延遲、帶寬、可靠性、能耗等方面的綜合性存儲服務(wù)能力也提出了更高的要求。傳統(tǒng)磁盤設(shè)備因內(nèi)部機(jī)械裝置受限, I/O帶寬已成為整個(gè)大規(guī)模存儲系統(tǒng)的主要瓶頸。閃存已經(jīng)以無可爭辯的低價(jià)格、高性能、非易失、低功耗等特點(diǎn)在性能上已對磁盤形成優(yōu)勢。另外,若要使用固態(tài)硬盤組成大規(guī)模存儲陣列,現(xiàn)有的幾種傳輸信道根本無法滿足帶寬需求。而相較于SAS、SATA、FC、iSCSI等存儲傳輸接口,PCIe具有更快的傳輸帶寬,完全能滿足大規(guī)模存儲陣列的帶寬要求。 本文主要對基于閃存的高速PCIe固態(tài)存儲卡進(jìn)行了研究與實(shí)現(xiàn),主要工作如下: 首先,,本文研究了閃存的存儲特性、芯片內(nèi)部結(jié)構(gòu)和接口,設(shè)計(jì)實(shí)現(xiàn)了閃存芯片控制器,使之能夠正確訪問閃存存儲芯片。 其次,本文對當(dāng)前閃存控制器的研究現(xiàn)狀進(jìn)行了詳盡分析,針對現(xiàn)有的閃存控制器對多通道和多die的并發(fā)性挖掘不夠深入的問題,提出了兩種閃存并行訪問策略,并分別為之設(shè)計(jì)實(shí)現(xiàn)了閃存控制器。實(shí)驗(yàn)結(jié)果表明,在多通道策略下,4通道獲得了2.1倍的加速比;采用亂序訪問之后,單片4die的IO帶寬利用率則達(dá)到了最少36%,最大167%的性能提升。 最后,本文研究了當(dāng)前主流存儲傳輸接口的發(fā)展趨勢,重點(diǎn)分析了PCIe總線接口的相關(guān)傳輸協(xié)議,并在事務(wù)層上對PCIe協(xié)議進(jìn)行解析,設(shè)計(jì)實(shí)現(xiàn)了DMA控制器,從而實(shí)現(xiàn)主機(jī)與固態(tài)存儲卡的數(shù)據(jù)傳輸。同時(shí),本文以采用高速PCIe1.1×4接口的FPGA開發(fā)板為平臺,使用三星公司的閃存芯片作為存儲單元,設(shè)計(jì)實(shí)現(xiàn)了基于閃存的具有PCIe接口、總?cè)萘繛?56GB、讀寫實(shí)測性能分別達(dá)到700MB/S和600MB/s高速固態(tài)存儲卡原型系統(tǒng)。
[Abstract]:With the rapid development of network, computing, storage and other technologies, today's world has gradually become the world of network, the world of data.The widespread emergence of data-intensive computing applications based on massive data, in addition to the huge demand for storage, performance, latency, bandwidth, reliability,Energy consumption and other aspects of the comprehensive storage service capacity also put forward higher requirements.Due to the limitation of internal mechanical devices, the I / O bandwidth of traditional disk devices has become the main bottleneck of the whole large-scale storage system.Flash memory has become an advantage over disk performance with indisputable features of low price, high performance, non volatile, low power consumption, etc.In addition, if the solid state hard disk is used to form a large storage array, the existing transmission channels can not meet the bandwidth requirements at all.Compared with the storage transport interface such as SASU SATAA FCU iSCSI, PCIe has faster transmission bandwidth and can meet the bandwidth requirements of large-scale storage arrays.In this paper, the high speed PCIe solid state memory card based on flash memory is studied and implemented. The main work is as follows:Firstly, the memory characteristics of flash memory, the internal structure and interface of flash memory are studied, and the controller of flash memory chip is designed and implemented so that it can access the memory chip correctly.Secondly, this paper makes a detailed analysis of the current research status of flash memory controller. Aiming at the problem that the existing flash memory controller is not deep enough to mine the concurrency of multi-channel and multi-, two parallel access strategies of flash memory are proposed.The flash memory controller is designed and implemented respectively.The experimental results show that the speedup ratio of 4 channels is 2.1 times under the multi-channel strategy, and the IO bandwidth utilization of monolithic 4die is at least 36%, with a maximum performance improvement of 167% after random access.Finally, this paper studies the development trend of current mainstream storage and transport interface, analyzes the related transport protocols of PCIe bus interface, analyzes the PCIe protocol on transaction layer, and designs and implements the DMA controller.Thus, the data transmission between host computer and solid state memory card is realized.At the same time, the FPGA development board with high speed PCIe1.1 脳 4 interface is used as the platform, the flash memory chip of Samsung is used as the memory unit, and the PCIe interface based on flash memory is designed and implemented.The total capacity is 256 GB. The performance of read and write is up to the prototype system of 700MB/S and 600MB/s high speed solid state memory card respectively.
【學(xué)位授予單位】:國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2012
【分類號】:TP333

【參考文獻(xiàn)】

相關(guān)期刊論文 前4條

1 徐小玲;IDE接口硬盤讀寫技術(shù)[J];電子科技大學(xué)學(xué)報(bào);2002年06期

2 ;P3Stor: A parallel, durable flash-based SSD for enterprise-scale storage systems[J];Science China(Information Sciences);2011年06期

3 吳昊,舒繼武,溫冬嬋,鄭緯民;Design and Implementation of a Fibre Channel Target Driver Supporting SCSI[J];Tsinghua Science and Technology;2005年01期

4 韓德志,王二梅,宋衛(wèi)國;SCSI總線技術(shù)概述[J];信陽師范學(xué)院學(xué)報(bào)(自然科學(xué)版);2000年03期



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