本文選題：無源 + 超高頻　； 參考：《南開大學(xué)》2013年博士論文

【摘要】：RFID(射頻識別)技術(shù)作為一種非接觸式無線自動識別技術(shù),其原理是通過射頻信號自動識別對象目標(biāo)而獲取相關(guān)數(shù)據(jù),識別工作過程中不需要人工干預(yù),被認(rèn)為是條形碼無線的版本。RFID技術(shù)作為物聯(lián)網(wǎng)的重要組成部分,隨著智慧城市等新興生活理念及科技理念的產(chǎn)生,它必將得到迅速的發(fā)展。近幾年,無線超高頻識別系統(tǒng)(UHF RFID)技術(shù)正在被迅速的應(yīng)用,特別是在供應(yīng)鏈、真假識別、車輛跟蹤、產(chǎn)品跟蹤等領(lǐng)域受到廣泛關(guān)注。同時嵌入式EEPROM系統(tǒng)作為電子標(biāo)簽重要要組成部分也廣泛應(yīng)用于這些領(lǐng)域。 本論文重點研究了無源超高頻射頻識別標(biāo)簽芯片模擬前端及EEPROM存儲器的設(shè)計。在論文的開始,論述了RFID系統(tǒng)整體架構(gòu)以及其RFID系統(tǒng)工作的原理,并且對與設(shè)計相關(guān)的協(xié)議標(biāo)準(zhǔn)進行了分析與比較。之后,對無源UHF超高頻無線射頻識別標(biāo)簽芯片的系統(tǒng)結(jié)構(gòu)進行了設(shè)計,對低功耗無源電子標(biāo)簽芯片設(shè)計中涉及到的關(guān)鍵技術(shù)進行了研究,對設(shè)計中的創(chuàng)新點進行了著重的闡述。首先提出一種低功耗的模擬前端解調(diào)電路設(shè)計。與傳統(tǒng)解調(diào)電路相比該解調(diào)電路結(jié)構(gòu)簡單,數(shù)據(jù)解調(diào)速度快。本文提出的電路結(jié)構(gòu)采用簡單的開關(guān)及反相器電路代替?zhèn)鹘y(tǒng)電路的濾波及比較器電路,在簡化電路結(jié)構(gòu)同時實現(xiàn)數(shù)據(jù)解調(diào),降低在解調(diào)數(shù)據(jù)過程中的功耗。之后,論文設(shè)計了一種存儲器控制時序電路,該電路可以完成在讀卡器發(fā)出指令及數(shù)據(jù)之后到對存儲器擦、寫或讀操作完成之前對存儲器電路的控制。與傳統(tǒng)電子標(biāo)簽架構(gòu)對存儲控制原理相比,電路減少了在對存儲器操作期間電子標(biāo)簽數(shù)字電路部分及模擬前端部分處于工作狀態(tài)的電路,其最大的作用是降低了電子標(biāo)簽在擦操作與寫操作期間的整體功耗。同時該電路結(jié)構(gòu)提高了存儲器工作穩(wěn)定性,實現(xiàn)存儲器在工作過程中完全獨立于外部電路,防止在對存儲器進行操作過程中由于通訊的意外中斷而導(dǎo)致對存儲器工作進程的影響。另外,論文提出了一種改進的存儲陣列結(jié)構(gòu),它可以克服傳統(tǒng)存儲結(jié)構(gòu)擦操作與寫操作必須分開進行的缺點,實現(xiàn)對存儲陣列的擦操作與寫操作同時進行,而且降低電路功耗,將每擦寫流程的工作時間降低一半,使電子標(biāo)簽工作時間縮短。論文設(shè)計了一種適用于無源UHF RFID電子標(biāo)簽芯片的測試及開發(fā)平臺,對電子標(biāo)簽芯片進行相關(guān)功能性驗證。該平臺可以直接與讀卡器通信進行測試,也可以與外部FPGA相連進行測試。論文主要研究放在無源UHF RFID電子標(biāo)簽芯片前端模擬電路的設(shè)計和EEPROM存儲器電路的系統(tǒng)結(jié)構(gòu)改造。本項目采用的工藝為0.18μm2P4M EEPROM進行流片,采用的通信協(xié)議為ISO/IEC18000-6標(biāo)準(zhǔn)。設(shè)計電路為具有低功耗高性能特性的UHF RFID電子標(biāo)簽。
[Abstract]:RFID (Radio Frequency Identification) technology as a non-contact wireless automatic identification technology, its principle is to automatically identify the object by radio frequency signals to obtain relevant data, the identification process does not require human intervention,As an important part of the Internet of things, RFID technology is considered to be the wireless version of bar code. With the emergence of new concepts of life and science and technology, such as intelligent city, it will be developed rapidly.In recent years, UHF RFIDs have been applied rapidly, especially in the fields of supply chain, true and false identification, vehicle tracking, product tracking and so on.At the same time, embedded EEPROM system as an important part of electronic label is also widely used in these fields.This paper focuses on the design of passive UHF RFID tag analog front end and EEPROM memory.At the beginning of the thesis, the whole architecture of RFID system and the principle of its RFID system are discussed, and the protocol standards related to the design are analyzed and compared.After that, the system structure of the passive UHF UHF RFID tag chip is designed, the key technologies involved in the design of the low power passive tag chip are studied, and the innovation points in the design are emphasized.A low-power analog front-end demodulation circuit is proposed.Compared with the traditional demodulation circuit, the structure of the demodulation circuit is simple and the speed of data demodulation is fast.In this paper, a simple switch and inverter circuit is used to replace the filter and comparator circuit of the traditional circuit, which can realize the data demodulation while simplifying the circuit structure and reduce the power consumption in the process of demodulation.After that, a memory control sequential circuit is designed, which can control the memory circuit after the reader sends out the instruction and data to the memory erasing, writing or reading operation.Compared with the traditional electronic tag architecture for storage control, the circuit reduces the electronic label digital circuit and analog front-end circuit in working state during the operation of the memory.The biggest effect is to reduce the overall power consumption of the tag during erasure and write operations.At the same time, the circuit structure improves the working stability of the memory and realizes that the memory is completely independent of the external circuit in the working process.To prevent the impact on the memory working process caused by the accidental interruption of communication during the operation of the memory.In addition, an improved memory array structure is proposed, which can overcome the shortcoming that the traditional memory structure erasure operation and write operation must be carried out separately, realize the erasure operation and write operation of the memory array simultaneously, and reduce the power consumption of the circuit.Reduce the working time of each erasure process by half, and shorten the working time of electronic label.A testing and developing platform for passive UHF RFID tag chip is designed in this paper.The platform can directly communicate with the card reader for testing, or can be connected to the external FPGA for testing.This paper mainly focuses on the design of analogue circuit in the front end of passive UHF RFID tag chip and the reconstruction of the system structure of EEPROM memory circuit.The process used in this project is 0.18 渭 m2P4M EEPROM for flow sheet, and the communication protocol is ISO/IEC18000-6 standard.The design circuit is UHF RFID tag with low power consumption and high performance.
【學(xué)位授予單位】：南開大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2013
【分類號】：TP391.44;TP333

【參考文獻】

相關(guān)期刊論文 前2條

1 程兆賢;戴宇杰;張小興;呂英杰;樊勃;;RFID中EEPROM時序及控制電路設(shè)計[J];微納電子技術(shù);2008年11期

2 程兆賢;張小興;戴宇杰;呂英杰;陳力穎;;0.18μm工藝小規(guī)模嵌入式EEPROM存儲陣列單Block電路[J];南開大學(xué)學(xué)報(自然科學(xué)版);2011年06期

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本文編號：1758340