本文選題：處理器陣列 + 容錯(cuò)技術(shù)�。� 參考：《天津工業(yè)大學(xué)》2017年碩士論文

【摘要】：目前超大規(guī)模集成電路技術(shù)把大量的處理器單元集成到單一芯片上,從而使用多處理器系統(tǒng)執(zhí)行很多大規(guī)模的并行任務(wù)。隨著VLSI陣列密度的增加,系統(tǒng)運(yùn)行期間PEs發(fā)生故障的概率也在增加。這些發(fā)生故障的PEs會(huì)破壞已有的網(wǎng)絡(luò)通訊結(jié)構(gòu),為了保證系統(tǒng)的穩(wěn)定性和可靠性,獲得無故障邏輯陣列的重構(gòu)技術(shù)成為有意義的研究課題。本文通過研究降階策略,針對(duì)快速重構(gòu)無故障邏輯陣列的問題,研究了處理器陣列上的快速重構(gòu),具體工作內(nèi)容如下:第一,文中提出了一個(gè)最短路徑段優(yōu)先擴(kuò)展的邏輯列重構(gòu)算法,該算法優(yōu)先擴(kuò)展最有可能生成最優(yōu)邏輯列的路徑段,即總是選擇當(dāng)前長(zhǎng)連接數(shù)最少的路徑段進(jìn)行擴(kuò)展,從而確保生成的邏輯列為最優(yōu)邏輯列。由于最優(yōu)邏輯列上的路徑段往往可以被率先擴(kuò)展到終點(diǎn),因此算法能夠更加快速地構(gòu)造出整個(gè)最優(yōu)邏輯列,并不需要計(jì)算相關(guān)區(qū)域所有PEs的路徑信息,從而克服了現(xiàn)有的動(dòng)態(tài)規(guī)劃算法需要計(jì)算所有無故障PEs的弱點(diǎn)。第二,在構(gòu)建好一個(gè)最優(yōu)邏輯整列后,處理器還是可能隨時(shí)出現(xiàn)故障,本文針對(duì)原有的邏輯陣列中發(fā)生實(shí)時(shí)故障下的陣列重構(gòu)問題,研究如何在實(shí)時(shí)故障下快速重構(gòu)一個(gè)盡可能大的新邏輯陣列。原有的處理方案在解決此問題時(shí),一般都會(huì)推翻原有的邏輯陣列結(jié)構(gòu),在整個(gè)主陣列的基礎(chǔ)上重新構(gòu)建最大的邏輯陣列。然而通過研究發(fā)現(xiàn),在某些情況下并不需要對(duì)整個(gè)主陣列進(jìn)行重構(gòu),就可得到一個(gè)相對(duì)大的邏輯陣列。因此,文中設(shè)計(jì)了一個(gè)有效的預(yù)處理技術(shù),可在局部區(qū)域產(chǎn)生一條最優(yōu)邏輯列來替換原有的包含實(shí)時(shí)故障PE的邏輯列。該技術(shù)并不需要對(duì)所有的邏輯列進(jìn)行構(gòu)建,因此可以快速的生成一個(gè)相對(duì)大的邏輯陣列,從而減少通訊延遲,節(jié)省網(wǎng)絡(luò)的資源消耗。
[Abstract]:At present, VLSI technology integrates a large number of processor units into a single chip, so that multiprocessor systems are used to perform many large-scale parallel tasks.With the increase of VLSI array density, the probability of PEs failure increases during system operation.These malfunctioning PEs will destroy the existing network communication structure. In order to ensure the stability and reliability of the system, obtaining the fault-free logic array reconstruction technology has become a meaningful research topic.In this paper, order reduction strategy is studied to solve the problem of fast reconstruction of fault-free logic array, and the fast reconfiguration on processor array is studied. The main work is as follows: first,In this paper, a logic sequence reconstruction algorithm with the shortest path segment first extended is proposed. The algorithm gives priority to the path segment that is most likely to generate the optimal logical sequence, that is, the path segment with the least number of connections is always selected for expansion.This ensures that the generated logic is an optimal logical column.Because the path segment on the optimal logic sequence can be extended to the end point first, the algorithm can construct the entire optimal logic sequence more quickly, without the need to calculate the path information of all the PEs in the related region.Therefore, it overcomes the weakness of the existing dynamic programming algorithm which needs to compute all the fault-free PEs.Second, after constructing an optimal logic sequence, the processor may fail at any time. This paper aims at the problem of array reconfiguration under the real-time fault in the original logic array.This paper studies how to reconstruct a new logic array as large as possible in real time fault.When the original processing scheme solves this problem, the original logical array structure will be overturned, and the largest logical array will be reconstructed on the basis of the whole main array.However, it is found that in some cases, a relatively large logical array can be obtained without the need to reconstruct the entire main array.Therefore, an effective preprocessing technique is designed to generate an optimal logic sequence in the local region to replace the original logic sequence containing the real time fault PE.This technique does not need to build all the logical columns, so it can quickly generate a relatively large logical array, thus reducing communication delay and saving network resource consumption.
【學(xué)位授予單位】：天津工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP332

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本文編號(hào)：1749302