本文選題：偽雙口RAM + 單口RAM　； 參考：《計算機輔助設(shè)計與圖形學(xué)學(xué)報》2017年02期

【摘要】：針對SoC中TP RAM的面積及功耗較大問題,提出一種優(yōu)化設(shè)計方法.該方法將SoC中的TP RAM替換成SP RAM,并在SP RAM外圍增加讀寫接口轉(zhuǎn)換邏輯,使替換后的RAM實現(xiàn)原TP RAM的功能,以保持對外接口不變.將文中方法應(yīng)用于一款多核SoC芯片,該芯片經(jīng)TSMC 28 nm HPM工藝成功流片,die size為10.7 mm×11.9 mm,功耗為17.2 W.測試結(jié)果表明,優(yōu)化后的RAM面積減少了24.4%,功耗降低了39%.
[Abstract]:In order to solve the problem of large area and power consumption of TP RAM in SoC, an optimal design method is proposed.In this method, TP RAM in SoC is replaced with SP RAM, and the conversion logic of read and write interface is added to the periphery of SP RAM, so that the replaced RAM can realize the function of original TP RAM so as to keep the external interface unchanged.The method is applied to a multi-core SoC chip. The chip is successfully fabricated by TSMC 28nm HPM process. The die size is 10.7mm 脳 11.9mm, and the power consumption is 17.2w.The test results show that the optimized RAM area is reduced by 24. 4 and the power consumption is reduced by 39.
【作者單位】： 西安培華學(xué)院中興電信學(xué)院;西安電子科技大學(xué)寬禁帶半導(dǎo)體材料與器件教育部重點實驗室;
【基金】：國家自然科學(xué)基金(61376099,6143000024) 陜西省教育廳專項基金項目(16JK2138)
【分類號】：TP333
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本文編號：1742744