發(fā)布時(shí)間：2018-04-11 06:27

  本文選題：FPGA + DDR　； 參考：《電子科技》2016年11期

【摘要】：為解決超高速采集系統(tǒng)中的數(shù)據(jù)緩存問(wèn)題,文中基于Xilinx Kintex-7 FPGA MIG_v1.9 IP核進(jìn)行了DDR3SDRAM控制器的編寫(xiě),分析并提出了提高帶寬利用率的方法。最終將其進(jìn)行類FIFO接口的封裝,屏蔽掉了DDR3 IP核復(fù)雜的用戶接口,為DDR3數(shù)據(jù)流緩存的實(shí)現(xiàn)提供便利。系統(tǒng)測(cè)試表明,該設(shè)計(jì)滿足大容量數(shù)據(jù)緩存要求,并具有較強(qiáng)的可移植性。
[Abstract]:In order to solve the problem of data cache in ultra-high speed acquisition system, the DDR3SDRAM controller is compiled based on Xilinx Kintex-7 FPGA MIG_v1.9 IP core, and the method of improving bandwidth utilization is analyzed and put forward.Finally, the FIFO interface is encapsulated, and the complex user interface of DDR3 IP core is shielded, which facilitates the implementation of DDR3 data stream cache.The system test shows that the design meets the requirement of large capacity data cache and has strong portability.
【作者單位】： 國(guó)防科學(xué)技術(shù)大學(xué)電子科學(xué)與工程學(xué)院;
【分類號(hào)】：TP333
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本文編號(hào)：1734806