本文選題：高通量測序技術(shù)　切入點(diǎn)：短序列比對　出處：《計(jì)算機(jī)研究與發(fā)展》2014年09期

【摘要】：自2008年1月高通量測序技術(shù)應(yīng)用以來,測序的通量和成本都在不斷下降.然而基因數(shù)據(jù)的爆發(fā)式增長速度已經(jīng)超過了摩爾定律,對海量數(shù)據(jù)的計(jì)算處理能力成為制約基因測序應(yīng)用推廣的瓶頸.以基于Hash索引的重測序算法為目標(biāo),對計(jì)算和訪存行為進(jìn)行分析,從而提出了一個(gè)現(xiàn)場可編程門陣列(field programmable gate array,FPGA)作為協(xié)處理器的架構(gòu),并在Convey公司的HC-1ex平臺(tái)上進(jìn)行了設(shè)計(jì)與實(shí)現(xiàn).其基本處理單元內(nèi)部采用全流水的設(shè)計(jì)及FIFO隔離計(jì)算模塊和訪存模塊,可以完整執(zhí)行重測序算法的核心流程.通過將基本處理單元和訪存端口的一對一綁定,在4塊Xilinx Virtex-6LX760上實(shí)現(xiàn)了64路并行處理流程,總平均讀內(nèi)存帶寬可達(dá)22.59GBps.與8核Intel Xeon處理器相比,可以提升28.5倍的性能.
[Abstract]:Since the application of high throughput sequencing technology in January 2008, the throughput and cost of sequencing have been decreasing.However, the explosive growth rate of gene data has exceeded Moore's law, and the computing ability of mass data has become the bottleneck of gene sequencing application.Based on the Hash index based resequencing algorithm, this paper analyzes the behavior of computing and memory access, and proposes a field programmable gate FPGA (FPGA) as a coprocessor, which is designed and implemented on the HC-1ex platform of Convey.In the basic processing unit, the core flow of the resequencing algorithm can be carried out completely by using the design of all income, the FIFO isolation calculation module and the memory access module.By binding the basic processing unit to the memory access port one-to-one, a 64-channel parallel processing flow is implemented on 4 Xilinx Virtex-6LX760. The total average read memory bandwidth can reach 22.59 GB / s.Compared with 8-core Intel Xeon processor, it can improve 28.5 times performance.
【作者單位】： 中國科學(xué)院計(jì)算技術(shù)研究所高性能計(jì)算機(jī)研究中心;中國科學(xué)院大學(xué);
【基金】：國家“九七三”重點(diǎn)基礎(chǔ)研究發(fā)展計(jì)劃基金項(xiàng)目(2012CB316502)
【分類號(hào)】：Q75;TP332

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