本文選題：ARM　切入點(diǎn)：FPGA　出處：《蘇州大學(xué)》2012年碩士論文

【摘要】：圖像處理技術(shù)在生物醫(yī)療、工業(yè)生產(chǎn)、軍事公安等領(lǐng)域有著廣泛應(yīng)用，傳統(tǒng)的圖像處理平臺(tái)多面向PC平臺(tái)，體積大，功耗高，開發(fā)復(fù)雜，微電子技術(shù)的飛速發(fā)展促進(jìn)圖像處理平臺(tái)朝著智能化、數(shù)字化、微型化方向發(fā)展，嵌入式系統(tǒng)的出現(xiàn)并且應(yīng)用在圖像處理平臺(tái)中，進(jìn)一步縮短圖像處理平臺(tái)二次開發(fā)周期，提高圖像處理平臺(tái)性能。 本文在研究多種嵌入式圖像處理平臺(tái)方案的基礎(chǔ)上，結(jié)合ARM核心板特點(diǎn)與FPGA開發(fā)技術(shù)提出基于ARM與FPGA的嵌入式實(shí)時(shí)圖像處理平臺(tái)設(shè)計(jì)方案，引入FPGA實(shí)現(xiàn)圖像處理平臺(tái)實(shí)時(shí)傳輸處理高分辨率圖像并且實(shí)現(xiàn)高分辨率圖像的大屏幕顯示，借助ARM硬件平臺(tái)首次在圖像處理平臺(tái)中引入嵌入式操作系統(tǒng)，大大簡(jiǎn)化實(shí)時(shí)圖像處理平臺(tái)應(yīng)用開發(fā)，為實(shí)時(shí)圖像處理平臺(tái)開發(fā)提供全新思路。 文中完成了由ARM主控制模塊、FPGA從模塊、實(shí)時(shí)圖像采集模塊組成的硬件電路設(shè)計(jì)，，采用S3C2440A ARM微處理器控制外圍接口與實(shí)時(shí)圖像采集模塊，采用EP1C3T144I7N FPGA芯片控制實(shí)時(shí)圖像的緩存、VGA接口時(shí)序以實(shí)現(xiàn)高分辨率實(shí)時(shí)圖像輸出，采用SAA7113H圖像解碼芯片實(shí)現(xiàn)模擬CCD的實(shí)時(shí)圖像采集與解碼；并且在自主設(shè)計(jì)的硬件平臺(tái)上嵌入經(jīng)個(gè)性化定制的Win CE嵌入式操作系統(tǒng)，設(shè)計(jì)基于Win CE系統(tǒng)的用于實(shí)時(shí)圖像采集的流接口驅(qū)動(dòng)程序；最后根據(jù)工業(yè)應(yīng)用領(lǐng)域需求，在設(shè)計(jì)好的軟、硬件平臺(tái)上運(yùn)行測(cè)量物體長(zhǎng)度的應(yīng)用軟件，驗(yàn)證了平臺(tái)的設(shè)計(jì)功能。 平臺(tái)集通用AV視頻接口、多個(gè)USB接口、RS-232串口、VGA接口于一體，實(shí)現(xiàn)圖像的實(shí)時(shí)采集與處理，輸出視頻圖像分辨率達(dá)800×600，60Hz。平臺(tái)采用模塊化的硬件設(shè)計(jì)與基于嵌入式操作系統(tǒng)的軟件設(shè)計(jì)，具有功能易擴(kuò)展，體積小，功耗低，移植便利，二次開發(fā)周期短的優(yōu)點(diǎn)。
[Abstract]:Image processing technology has been widely used in biomedical, industrial production, military and public security fields. Traditional image processing platforms are mostly PC oriented, large in volume, high in power consumption and complex in development.The rapid development of microelectronics technology promotes the development of image processing platform in the direction of intelligence, digitization and miniaturization. The emergence of embedded system and its application in image processing platform further shorten the second development period of image processing platform.Improve the performance of image processing platform.Based on the research of various embedded image processing platform schemes, this paper proposes a design scheme of embedded real-time image processing platform based on ARM and FPGA, combined with the characteristics of ARM core board and FPGA development technology.FPGA is introduced to realize the real-time transmission and processing of high-resolution images and the large screen display of high-resolution images. The embedded operating system is introduced into the image processing platform for the first time with the help of the ARM hardware platform.It greatly simplifies the application and development of real-time image processing platform and provides a new idea for the development of real-time image processing platform.In this paper, the hardware circuit is designed which is composed of ARM slave module and real time image acquisition module. The peripheral interface and real time image acquisition module are controlled by S3C2440A ARM microprocessor.EP1C3T144I7N FPGA chip is used to control the timing of real-time image buffer interface to realize high resolution real-time image output, and SAA7113H image decoding chip is used to realize real-time image acquisition and decoding of simulated CCD.And embed the customized Win CE embedded operating system on the self-designed hardware platform, designed the stream interface driver for real-time image acquisition based on the Win CE system. Finally, according to the requirements of the industrial application field,The design function of the platform is verified by running the application software of measuring the object length on the designed software and hardware platform.The platform integrates general AV video interface and several USB interfaces with RS-232 serial port and VGA interface. The real-time image acquisition and processing are realized. The resolution of output video image reaches 800 脳 600,60Hz.The platform adopts modularized hardware design and software design based on embedded operating system, which has the advantages of easy expansion, small volume, low power consumption, convenient transplantation and short secondary development cycle.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP368.1;TP391.41

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 宋敏,鄶新凱,鄭亞茹;CCD與CMOS圖像傳感器探測(cè)性能比較[J];半導(dǎo)體光電;2005年01期

相關(guān)碩士學(xué)位論文 前2條

1 周茉;基于ARM+FPGA的嵌入式數(shù)控裝置研究[D];大連交通大學(xué);2010年

2 王夷恬;嵌入式視頻監(jiān)控系統(tǒng)的FPGA圖像處理子系統(tǒng)設(shè)計(jì)[D];南京理工大學(xué);2009年

本文編號(hào)：1711140