本文選題：SoC　切入點：PLB總線　出處：《西安電子科技大學》2013年碩士論文

【摘要】：隨著集成電路的高速發(fā)展，，SoC（System on Chip）技術已經成為當今重要的發(fā)展方向。特別是基于各種IP核，可重用的SoC設計方法的出現(xiàn)，使得總線接口設計技術在高效且具有良好擴展性和兼容性的總線平臺上顯得意義非凡�？偩€及其接口技術決定了整個SoC的效率，效率不夠高從根本上會削弱系統(tǒng)的性能，同時復雜的結構占用了本來大量有限的片上系統(tǒng)資源。所以，總線的選擇對于SoC來講至關重要，通過對當今流行的CoreConnect總線，AMBA總線，Wishbone總線以及OCP總線之間的比較，了解所需總線的特征，設計出適用的橋接器。 SoC芯片內各個IP模塊通過片內高速總線進行互連，目前多種SoC總線協(xié)議的并存，使得IP核之間的復用變得困難。本文采用Verilog HDL設計實現(xiàn)一種高效的SoC總線協(xié)議橋接器，通過Wishbone從設備可與PLB總線有效結合，從而實現(xiàn)高速PLB總線到可自定義仲裁方式的Wishbone總線之間的協(xié)議標準轉換，從而使PLB總線和Wishbone總線IP核的可復用性得到提高。在本文設計中，通過對FIFO的讀、寫保持了橋接器數(shù)據(jù)讀寫的一致，同時為實現(xiàn)時序的同步采用了異步電路握手控制方式。 盡管Xilinx公司在其EDK設計工具中對于較為復雜的PLB總線，利用其向導工具生成一套專門為用戶服務的接口模塊，但它還存在一定的局限性，比如結構復雜、效率低下、片上系統(tǒng)資源占用較多等。因此對于研發(fā)自主知識產權的核心技術以及應用開發(fā)這方面的工作很有必要。本文針對PLB總線與Wishbone總線的互連接口如何實現(xiàn)讀寫，以及如何解決跨時鐘域等問題，提出了設計方案，采用VerilogHDL進行設計并用Modelsim進行了仿真驗證，得到的結果是該橋接器能夠正確運行在系統(tǒng)中且能訪問其他片上資源，同時使設計功能得到實現(xiàn)。
[Abstract]:With the rapid development of integrated circuits, SoCon system on Chip technology has become an important direction of development.Especially, the emergence of reusable SoC design method based on various IP cores makes the bus interface design technology very significant on the bus platform with high efficiency and good extensibility and compatibility.Bus and its interface technology determine the efficiency of the whole SoC, which can weaken the performance of the system fundamentally, and the complex structure takes up a large number of limited on-chip system resources.Therefore, the choice of bus is very important for SoC. By comparing the popular CoreConnect bus, Wishbone bus and OCP bus, we can find out the characteristics of the required bus and design a suitable bridge.Each IP module in SoC chip is interlinked by high speed bus. At present, the coexistence of various SoC bus protocols makes it difficult to reuse IP cores.In this paper, Verilog HDL is used to design and implement an efficient SoC bus protocol bridge, which can be effectively combined with PLB bus through Wishbone, so that the protocol standard conversion between high speed PLB bus and Wishbone bus with custom arbitration mode can be realized.Thus, the reusability of PLB bus and Wishbone bus IP core is improved.In the design of this paper, by reading the FIFO, the writer keeps the same data reading and writing of the bridge. At the same time, the asynchronous circuit handshake control mode is used to realize the timing synchronism.Although Xilinx used its wizard tools to generate a set of interface modules for the more complex PLB bus in its EDK design tools, it still has some limitations, such as complex structure and low efficiency.On-chip system resources occupy more and so on.Therefore, it is necessary to research and develop the core technology and application of intellectual property rights.In this paper, aiming at how to realize the interface between PLB bus and Wishbone bus, how to read and write, and how to solve the problem of cross-clock domain, this paper proposes a design scheme, which is designed by VerilogHDL and simulated by Modelsim.The result is that the bridge can run correctly in the system and can access other on-chip resources, at the same time, the design function can be realized.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP336;TN47

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