本文選題：SOC　切入點(diǎn)：調(diào)試　出處：《武漢紡織大學(xué)》2013年碩士論文

【摘要】：隨著片上系統(tǒng)（SOC）技術(shù)的不斷發(fā)展以及嵌入式系統(tǒng)對處理器處理能力的要求不斷提到。32位處理器IP核已經(jīng)廣泛用于SOC及SOPC（硬件可配置SOC）的設(shè)計(jì)與開發(fā)當(dāng)中，在眾多的嵌入式處理器中，專用指令集處理器(ASIP，application Specific in-struction processor)設(shè)計(jì)是多年來嵌入式系統(tǒng)研究的熱點(diǎn)，因?yàn)槿诤狭嗽S多先進(jìn)微處理器設(shè)計(jì)方法和技術(shù)，并可以在滿足功能的同時(shí)縮短嵌入式微處理的研發(fā)時(shí)間。但是采用ASIP設(shè)計(jì)出來的嵌入式系統(tǒng)的復(fù)雜度與開發(fā)設(shè)計(jì)難度也會隨之不斷的增加，這對嵌入式系統(tǒng)的設(shè)計(jì)與開發(fā)提出了新的要求，，所以調(diào)試在ASIP的開發(fā)中就越來越重要了，隨著OCD（On Chip Debugging:在芯片調(diào)試）調(diào)試方式與SOC技術(shù)的出現(xiàn)，完全改變了傳統(tǒng)的“仿真器加編程器”的調(diào)試方法，通過這種方式可以提高整體調(diào)試的效率。本文首先以O(shè)penrisc CPU作為嵌入式處理器的研究模型，在這個(gè)CPU基礎(chǔ)上添加外圍接口設(shè)計(jì)出一個(gè)SOC最小系統(tǒng)并在深入研究SOC設(shè)計(jì)理念和JTAG調(diào)試原理后，采用軟硬件協(xié)同設(shè)計(jì)方法，充分利用SOC的可重用性與FPGA的可編程性，在SOC系統(tǒng)中利用片上總線技術(shù)加入了自己編寫的針對SOC嵌入式處理器調(diào)試接口的IP core,通過這個(gè)IP core可以方便的進(jìn)行嵌入式處理器的調(diào)試以及嵌入式軟件的調(diào)試。通過采用這種調(diào)試方式達(dá)到調(diào)試SOC硬件也可以調(diào)試嵌入式軟件的目的。同時(shí)在Linux系統(tǒng)中針對ASIP進(jìn)行Linux系統(tǒng)移植并采用JTAG方式進(jìn)行系統(tǒng)的下載。
[Abstract]:With the continuous development of on-chip system (SOC) technology and the requirement of embedded system for processor processing capability, the .32-bit processor IP core has been widely used in the design and development of SOC and SOPC (hardware configurable SOCC). Among many embedded processors, the design of ASIP application Specific in-struction processor has been a hot spot in embedded system research for many years, because of the integration of many advanced microprocessor design methods and techniques. It can also shorten the development time of embedded microprocessing while satisfying the function. However, the complexity of embedded system designed by ASIP and the difficulty of developing and designing will increase with it. This has put forward new requirements for the design and development of embedded system, so debugging is becoming more and more important in the development of ASIP. With the emergence of OCD(On Chip debugging (debugging in Chip) and SOC technology, The traditional debugging method of "emulator plus programmer" is completely changed, by which the overall debugging efficiency can be improved. Firstly, Openrisc CPU is used as the research model of embedded processor. On the basis of this CPU, a SOC minimum system is designed by adding peripheral interface. After deeply studying the SOC design concept and JTAG debugging principle, the hardware / software co-design method is adopted to make full use of the reusability of SOC and the programmability of FPGA. In the SOC system, the on-chip bus technology is used to add IP core for the debugging interface of SOC embedded processor, through which the embedded processor can be debugged and embedded software can be debugged conveniently. The embedded software can also be debugged by using this debugging method to debug the SOC hardware. At the same time, the Linux system is transplanted to ASIP in the Linux system and the system is downloaded by JTAG mode.
【學(xué)位授予單位】：武漢紡織大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP368.1;TN47

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本文編號：1693112