發(fā)布時(shí)間：2018-03-26 21:23

  本文選題：大容量緩存　切入點(diǎn)：數(shù)據(jù)壓縮　出處：《中北大學(xué)》2013年碩士論文

【摘要】：在航天領(lǐng)域，壓縮是解決海量數(shù)據(jù)給有限信道帶寬帶來(lái)壓力的主要措施之一，遙感圖像因其獲取代價(jià)很高所以特別珍貴，也給壓縮技術(shù)帶來(lái)了巨大的挑戰(zhàn)，如何能即提高壓縮比，又能保證還原后的圖像與原始圖像差距不大是當(dāng)前壓縮技術(shù)的主要發(fā)展目標(biāo)。目前，JPEG2000圖像壓縮標(biāo)準(zhǔn)很好的解決了現(xiàn)有的矛盾。為滿足特殊領(lǐng)域?qū)?shù)據(jù)實(shí)時(shí)性的要求，大容量的緩存FIFO的設(shè)計(jì)也是一個(gè)熱門的研究方向。 本文首先介紹了數(shù)據(jù)緩存壓縮的發(fā)展現(xiàn)狀與應(yīng)用領(lǐng)域，針對(duì)任務(wù)要求，確定了以Altera公司的Cyclone II（颶風(fēng)II）系列FPGA為邏輯控制芯片，以兩片SDRAM為緩存介質(zhì)構(gòu)造乒乓操作來(lái)緩存上游下發(fā)的數(shù)據(jù)，以美國(guó)ADI公司的JPEG2000專用芯片ADV212實(shí)現(xiàn)對(duì)數(shù)據(jù)的壓縮的總體設(shè)計(jì)方案。本文詳細(xì)介紹了大容量緩存和數(shù)據(jù)壓縮各功能單元的構(gòu)成和操作原理，采用簡(jiǎn)化的SDRAM控制器狀態(tài)機(jī)來(lái)減少編程的復(fù)雜度。本文對(duì)關(guān)鍵的ADV212固件文件數(shù)據(jù)采取調(diào)用QuartusⅡ中提供的雙端口RAM IP核，加載mif固件文件的方式，大大簡(jiǎn)化了VHDL程序的設(shè)計(jì)難度。為了保證緩存芯片SDRAM運(yùn)行的可靠性，本設(shè)計(jì)在PCB布板方面采取了對(duì)數(shù)據(jù)線等長(zhǎng)布線的操作，重要控制信號(hào)線上串聯(lián)33的電阻，，消除干擾。 論文最后對(duì)裝置各模塊的功能進(jìn)行了測(cè)試，并分析了緩存芯片中所讀取的數(shù)據(jù)，對(duì)壓縮后的數(shù)據(jù)進(jìn)行了還原，結(jié)果表明，本文設(shè)計(jì)的緩存壓縮裝置滿足要求，而且具有很高的實(shí)用意義。
[Abstract]:In the aerospace field, compression is one of the main measures to solve the pressure of mass data on the limited channel bandwidth. Remote sensing image is extremely valuable because of its high cost, and it also brings great challenges to compression technology. How to increase the compression ratio, At present, JPEG2000 image compression standard has solved the existing contradiction well. In order to meet the requirement of real-time data in special field, JPEG2000 image compression standard can ensure that the difference between the original image and the restored image is not big. The design of large-capacity cache FIFO is also a hot research direction. In this paper, the development and application of data cache compression are introduced. According to the task requirements, Altera Cyclone II series FPGA is chosen as the logic control chip. The ping-pong operation is constructed with two pieces of SDRAM as the buffer medium to cache the data sent down upstream, This paper introduces the structure and operation principle of each function unit of large capacity cache and data compression in detail. The state machine of simplified SDRAM controller is used to reduce the complexity of programming. In this paper, the key data of ADV212 firmware file is loaded by calling the dual-port RAM IP core provided in Quartus 鈪

本文編號(hào)：1669663