本文選題：功能驗證　切入點：斷言　出處：《哈爾濱工業(yè)大學(xué)》2012年碩士論文

【摘要】：隨著數(shù)字電路系統(tǒng)的功能日趨復(fù)雜，使電路或系統(tǒng)的功能驗證難度逐漸增加。目前，在芯片開發(fā)全流程中，功能驗證占用的資源占到全部開發(fā)資源約70%到90%左右，而RTL級的驗證約占全部驗證工作的50%。說明RTL級驗證已經(jīng)成為芯片設(shè)計過程中的重大瓶頸之一。 以覆蓋率驅(qū)動的驗證方法是通過受約束的隨機矢量激勵輸入到待驗證模塊（DUV），根據(jù)輸出的結(jié)果來分析待驗證模塊的功能是否正確。采用這種方式的好處是可以較為方便的覆蓋一個很大的驗證空間，同時可以輸入多次不同的激勵，而逐漸覆蓋到邊緣情況。但是，上述方式在實際使用中依舊存在著缺陷，對仿真波形的分析及輸出端口檢查，短時間內(nèi)不能準確定位設(shè)計錯誤之處，時間花費多，可觀測性不強，不容易覆蓋邊緣。 本文首先對現(xiàn)今主要的驗證方法進行分析，闡述了以覆蓋率為驅(qū)動的驗證工作中遇見的困難，以及其必然的不足之處。針對復(fù)雜芯片驗證中的困難，采用結(jié)合斷言的以覆蓋率驅(qū)動的驗證方法。結(jié)合斷言驗證，可增強驗證輸出結(jié)果的可觀測性，，及驗證過程的可控性，從而彌補覆蓋率驅(qū)動驗證的不足。有利于較快的發(fā)現(xiàn)設(shè)計錯誤，縮短仿真測試周期，降低遺漏設(shè)計缺陷概率。之后本文對當(dāng)下主流斷言驗證的語言進行分析，確定使用SVA作為驗證工具。分析了使用SVA構(gòu)建USB2.0控制器待驗證環(huán)境的過程。本文采用的將兩種驗證方法相結(jié)合的方案，可有效提高驗證工作的效率，從而縮減驗證周期。 最后，本文對驗證輸出結(jié)果進行了全面分析。對比結(jié)合斷言的覆蓋率驅(qū)動和只使用覆蓋率為驅(qū)動兩種驗證方法的輸出結(jié)果，可見前者節(jié)約了大量的驗證時間。
[Abstract]:With the increasing complexity of the functions of digital circuit systems, the difficulty of functional verification of circuits or systems increases gradually. At present, in the whole process of chip development, functional verification occupies about 70% to 90% of the total development resources. The verification of RTL level accounts for about 50% of the whole verification work. It shows that RTL level verification has become one of the major bottlenecks in the chip design process. The verification method driven by coverage is to input the constrained random vector excitation to the module to be verified. According to the output results, the function of the module to be verified is analyzed. The advantage of this method is that it can be compared with that of the model. To easily cover a large verification space, At the same time, different excitation can be input several times, and gradually cover the edge case. However, the above method still has some defects in practical use, the analysis of the simulation waveform and the inspection of the output port, In a short period of time, it can not accurately locate the design errors, time is more expensive, observability is not strong, it is not easy to cover the edge. In this paper, the main verification methods are analyzed, and the difficulties encountered in the verification work driven by coverage are expounded, as well as the necessary shortcomings. In view of the difficulties in the verification of complex chips, Combined with assertion verification, the observability of the verification output and the controllability of the verification process can be enhanced. In order to make up for the lack of coverage driven verification, it is helpful to find design errors quickly, shorten the period of simulation test, and reduce the probability of missing design defects. Using SVA as the verification tool, this paper analyzes the process of using SVA to build the USB2.0 controller to be verified. The method of combining the two verification methods in this paper can effectively improve the efficiency of the verification work and thus reduce the verification period. Finally, this paper makes a comprehensive analysis of the verification output results. Comparing the results of the two verification methods, the coverage driven method combined with the assertion and only using coverage as the driving method, the former saves a lot of verification time.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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