發(fā)布時(shí)間：2018-03-21 09:07

  本文選題：高速緩存　切入點(diǎn)：低功耗　出處：《浙江大學(xué)》2012年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著智能手機(jī)、平板電腦等移動(dòng)設(shè)備的盛行,低功耗已成為處理器必不可少的屬性,高速緩存作為處理器的主要功耗來(lái)源之一,其低功耗設(shè)計(jì)的需要日益突出。本文提出并研究了三種路預(yù)測(cè)訪問(wèn)方案,以較少的附加資源,減少高速緩存訪問(wèn)的功耗,同時(shí)降低帶來(lái)的性能損失。本文的主要研究?jī)?nèi)容和創(chuàng)新點(diǎn)包括： 1、基于指令的高速緩存分類(lèi)路預(yù)測(cè)。在充分研究各種指令和路預(yù)測(cè)信息源關(guān)系的基礎(chǔ)上,將指令根據(jù)所需預(yù)測(cè)源的不同進(jìn)行劃分,并結(jié)合處理器不同流水線階段的指令信息,從多個(gè)預(yù)測(cè)源中選取所需的預(yù)測(cè)路信息。之后研究程序中各種指令的比例,以較少的附加預(yù)測(cè)資源和性能損失節(jié)省較大的功耗,同時(shí)通過(guò)實(shí)驗(yàn)分析各種預(yù)測(cè)源中資源與預(yù)測(cè)效率、功耗、性能之間的關(guān)系,以得到最佳的預(yù)測(cè)資源配置。該方案能夠很好的降低緩存功耗,但附加資源稍大,性能損失也較多。 2、基于循環(huán)的高速緩存單路徑路預(yù)測(cè)。首先根據(jù)預(yù)測(cè)基于歷史的性質(zhì),分析了分類(lèi)路預(yù)測(cè)的缺點(diǎn),提出了基于循環(huán)的單路徑路預(yù)測(cè)。該方案以循環(huán)作為路預(yù)測(cè)開(kāi)啟的先決條件,只在遇到循環(huán)且該循環(huán)已被記錄的情況下,方才開(kāi)啟路預(yù)測(cè)。之后通過(guò)實(shí)驗(yàn)分析了單路徑路預(yù)測(cè)系統(tǒng)中資源分配與預(yù)測(cè)效率的關(guān)系,并證實(shí)了該預(yù)測(cè)方案亦能很好的降低緩存功耗,且附加資源和性能損失皆大幅下降。 3、基于循環(huán)的高速緩存多路徑路預(yù)測(cè)。通過(guò)在循環(huán)中使用多個(gè)路徑的方法,解決了循環(huán)中因分支指令存在而造成的多個(gè)路徑之間相互沖突的現(xiàn)象,并分析程序中分支指令與循環(huán)的數(shù)量,提出最佳的路徑個(gè)數(shù),并通過(guò)實(shí)驗(yàn)驗(yàn)證在資源足夠的情況下,相同資源配置的多路徑路預(yù)測(cè)優(yōu)于單路徑路預(yù)測(cè),尤其是性能損失得到了更大的降低。
[Abstract]:With the popularity of mobile devices such as smart phones and tablets, low power consumption has become an essential attribute of processors. Cache is one of the main power sources of processors. In order to reduce the power consumption of cache access, we propose and study three kinds of path predictive access schemes to reduce the power consumption of cache access. At the same time, reduce the performance loss. The main contents and innovations of this paper include:. 1. Cache classified path prediction based on instruction. On the basis of fully studying the relationship between various kinds of instructions and path prediction information sources, the instructions are divided according to the different prediction sources needed, and the instruction information of different stages of pipeline processor is combined. The required prediction path information is selected from multiple prediction sources. After that, the proportion of instructions in the program is studied to save large power consumption with less additional prediction resources and performance loss. At the same time, the relationship between resource and prediction efficiency, power consumption and performance is analyzed through experiments to obtain the best predictive resource allocation. This scheme can reduce cache power consumption well, but the additional resources are slightly larger, and the performance loss is more. (2) Cache single path prediction based on cycle. Firstly, according to the properties of prediction based on history, the shortcomings of classifying path prediction are analyzed, and a single path prediction based on cycle is proposed. Only when the cycle is encountered and the cycle has been recorded, the path prediction is opened. Then, the relationship between resource allocation and prediction efficiency in a single path prediction system is analyzed through experiments. It is proved that the proposed scheme can also reduce cache power consumption, and the loss of additional resources and performance are greatly reduced. 3. Cache multipath prediction based on loop. By using multiple paths in the loop, the conflict between multiple paths caused by branch instructions in the loop is solved. The number of branch instructions and loops in the program is analyzed, and the optimal number of paths is put forward. The experimental results show that the multi-path prediction of the same resource allocation is better than that of single-path prediction in the case of sufficient resources. In particular, the performance loss has been further reduced.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類(lèi)號(hào)】：TP333

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本文編號(hào)：1643176