本文選題：阻變存儲器　切入點：存儲單元　出處：《復(fù)旦大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著特征尺寸的不斷減小,傳統(tǒng)的Flash會遇到其工藝瓶頸。尋找下一代新型存儲器成為研究的熱點。在眾多下一代非易失性存儲器中,阻變存儲器(RRAM)由于其邏輯兼容性、編程電壓低、易于高密度集成等優(yōu)點迅速成為下一代新型存儲器的有力競爭者。 RRAM芯片為全定制設(shè)計,其存儲單元的版圖結(jié)構(gòu)和其他模塊版圖的布局、布線,都會嚴(yán)重影響到芯片面積和阻變性能,所以設(shè)計出良好的阻變存儲器的版圖對整個芯片的設(shè)計有著極其重要的影響。針對這種情況,本文主要研究RRAM芯片的版圖設(shè)計,在此基礎(chǔ)上研究阻變單元編程電壓、高低阻分布、數(shù)據(jù)保持能力等的關(guān)系,并對其進(jìn)行了優(yōu)化,最終使芯片面積和性能達(dá)到最優(yōu)。 本文設(shè)計了一款容量為32kb,阻變材料為WOx,采用1T1R結(jié)構(gòu)的阻變存儲器。主要內(nèi)容有：首先分析芯片設(shè)計目標(biāo)和要求,其次分析選取合適的選通管并設(shè)計最小尺寸的RRAM cell的結(jié)構(gòu),再根據(jù)cell結(jié)構(gòu),考慮寄生參數(shù)如寄生電阻、寄生電容的影響,設(shè)計面積和可靠性折中的陣列結(jié)構(gòu)。然后由設(shè)計要求設(shè)計最簡單、可靠性最高的外圍電路包括行列譯碼器、DMA等模塊,并仿真驗證�？偲磿r使行列譯碼器與陣列節(jié)點匹配和各模塊的版圖拼接時優(yōu)化布局,使得面積最小。最后介紹了I/O PAD的選取和testkey的設(shè)計。 最終芯片在HHNEC0.5um工藝線上流片。通過對芯片的測試,阻變單元性能良好,高低阻窗口可達(dá)到10倍以上,編程電壓和數(shù)據(jù)保持能力均達(dá)到初始設(shè)計和實際應(yīng)用要求。說明良好的版圖設(shè)計可以使芯片的面積得到優(yōu)化,性能得到保障。
[Abstract]:With the decrease of feature size, the traditional Flash will meet with its technological bottleneck. Finding the next generation of new memory has become a research hotspot. In many of the next generation non-volatile memory, resistive memory (RRAM) is due to its logical compatibility. The advantages of low programming voltage and easy high density integration have become powerful competitors for the next generation of memory. The RRAM chip is designed for full customization. The layout structure of the memory unit and the layout and wiring of other modules will seriously affect the chip area and resistive performance. Therefore, the design of good resistive memory layout has an extremely important impact on the design of the whole chip. In view of this situation, this paper mainly studies the layout design of RRAM chip, on the basis of which, the programming voltage of resistive unit is studied. The relationship between high and low resistive distribution, data retention ability and so on is optimized, and the chip area and performance are optimized. In this paper, a kind of resistive memory with 32kb capacity, WOx-resistant material and 1T1R structure is designed. The main contents are as follows: firstly, the design objectives and requirements of the chip are analyzed; secondly, the structure of the RRAM cell with the minimum size is analyzed and the appropriate gating tube is selected. Then according to the cell structure, considering the parasitic parameters such as parasitic resistance, parasitic capacitance, design area and reliability of the eclectic array structure. The peripheral circuit with the highest reliability includes the modules such as the row and row decoder and DMA, and the simulation verifies that the total spell time makes the row and column decoder match with the array node and the layout of each module is optimized. Finally, the selection of I / O PAD and the design of testkey are introduced. Finally, the chip flows on the HHNEC0.5um process line. By testing the chip, the performance of the resistive unit is good, and the high and low resistive window can reach more than 10 times. Both the programming voltage and the data retention ability meet the requirements of initial design and practical application. It is shown that good layout design can optimize the chip area and ensure the performance.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333

【共引文獻(xiàn)】

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1 史鵬,姚熹,吳小清,張良瑩;PZT鐵電薄膜刻蝕的研究進(jìn)展[J];壓電與聲光;2003年05期

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