本文選題：柵極干擾　切入點：側(cè)壁隔離層　出處：《半導(dǎo)體技術(shù)》2017年12期 　論文類型：期刊論文

【摘要】：為了研究側(cè)壁隔離層對閃存器件可靠性的影響,分別制備了Si_3N_4和SiO_2-Si_3N_4-SiO_2-Si_3N_4(ONON)復(fù)合層作為柵側(cè)壁隔離層的45 nm或非閃存(NOR flash)器件,對編程后、循環(huán)擦寫后的閃存器進(jìn)行柵極干擾的測試,討論了不同柵側(cè)壁隔離層對柵極干擾的影響。結(jié)果表明,雖然純氧化硅隔離層可減少NOR自對準(zhǔn)接觸孔(SAC)刻蝕時對側(cè)壁隔離層的損傷,但其在柵極干擾時在氧化物-氮化物-氧化物(ONO)處有更高的電場,從而在柵干擾后閾值電壓變化較大,且由于在擦寫操作過程中會陷入電荷,這些電荷在大的柵極電壓和長時間的柵干擾作用下均會對閃存器的可靠性產(chǎn)生負(fù)面的影響。ONON隔離層的閃存器無可靠性失效。因此以O(shè)NON作為側(cè)壁隔離層比以純氮化硅作為側(cè)壁隔離層的閃存器件具有更好的柵干擾性能。
[Abstract]:In order to study the effect of sidewall isolation layer on the reliability of flash memory devices, Si_3N_4 and SiO _ 2-Si3N _ 4-SiO _ 2-Si _ 3N _ 4-SiO _ 2-S _ 3N _ 4 / ONON composite layers were fabricated, respectively, as 45 nm or non-flash side wall isolating layers of gate side wall isolators. After programming, the gate interference of the circularly erased flash memory was tested. The effects of different gate side wall isolation layers on gate interference are discussed. The results show that although the pure silicon oxide insulator can reduce the damage to the side wall isolation layer during the etching of the NOR self-aligned contact hole, However, it has a higher electric field at the oxide nitride oxide Ono when the gate interferes, so the threshold voltage changes greatly after the gate interference, and because of the charge in the scribing operation, These charges have negative effect on the reliability of flash memory under the action of large gate voltage and long time gate interference. The flash memory in the ONON isolation layer has no reliability failure. Therefore, the ratio of ONON as side wall isolation layer to pure nitridation is used as the side wall isolation layer. The flash memory device with silicon as the side wall insulator has better gate interference performance.
【作者單位】： 中芯國際集成電路制造有限公司;
【分類號】：TP333
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本文編號：1641155