本文選題：二級Cache　切入點：物理設(shè)計　出處：《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：YHFT-DX是在65nm工藝下設(shè)計的一款高性能DSP（Digital Signal Processor）芯片，，要求在最差工藝條件下達到800MHz的設(shè)計目標。作為芯片存儲通路的中心樞紐，二級Cache的設(shè)計至關(guān)重要。本文研究了YHFT-DX初樣芯片和正樣芯片中二級Cache的物理設(shè)計優(yōu)化技術(shù)。主要內(nèi)容分為如下幾點： 1）二級Cache采用分體結(jié)構(gòu)，將1MB的存儲體分成16個Bank體，每個Bank體由4個SRAM_CELL基本模塊構(gòu)成。研究了SRAM_CELL模塊的電路設(shè)計，優(yōu)化了其布局結(jié)構(gòu)、布線方法以及譯碼電路，最后合理規(guī)劃了該模塊的版圖布局。 2）研究了初樣芯片中宏模塊Bank體的物理設(shè)計，使用了原地優(yōu)化等多種方法進行時序收斂，而且采用了有用偏差技術(shù)優(yōu)化了長互連路徑的時序。研究了全芯片中Bank體的布局結(jié)構(gòu)，分析了不同布局結(jié)構(gòu)的關(guān)鍵路徑和性能上的優(yōu)缺點，最終確定了初樣芯片中Bank體的倒U型布局結(jié)構(gòu)。 3）對LRU（Least Recent Use）模塊進行全定制設(shè)計，使用了帶復(fù)位端的13T存儲單元，并在面積、性能、噪聲容限和功耗等各個方面與其他存儲單元進行了比較分析。設(shè)計了讀寫操作電路，其中讀操作電路全部采用組合邏輯實現(xiàn)。模擬了延時和功耗結(jié)果，全定制設(shè)計將關(guān)鍵路徑延時減少218ps，時序性能提高了29%，消除了芯片中與LRU相關(guān)的時序違反。 4）使用層次化設(shè)計方法進行正樣芯片二級Cache的物理設(shè)計。重新調(diào)整了Bank體的布局結(jié)構(gòu)，根據(jù)與全芯片中其他模塊的互連關(guān)系優(yōu)化了I/O端口的位置，改善了跨模塊路徑80的時序。設(shè)計了電源網(wǎng)絡(luò)，在保證供電充足的同時將電壓降控制在3%以內(nèi)。時鐘樹綜合采用了平衡樹的二叉樹拓撲結(jié)構(gòu)，并且使用了多種方法來優(yōu)化時鐘偏差和噪聲。分析了串擾對信號延遲的影響，對串擾預(yù)防和修復(fù)的方法進行了研究，有效提高了設(shè)計的抗噪聲能力。 5）在正樣芯片中重組了存儲體的層次結(jié)構(gòu)，將兩個Bank體合并為單個Bank2模塊，規(guī)劃了遠端存儲單元的長互連，并采用了雙倍線寬雙倍間距的布線規(guī)則，改善關(guān)鍵路徑延時30，有效解決了二級Cache中因長互連線引起的時序違反。 最終，與初樣芯片相比，正樣芯片的二級Cache延時減少90，性能提高6.7%，在65nm最差工藝條件下達到了800MHz的設(shè)計目標。
[Abstract]:YHFT-DX is a high performance DSP(Digital Signal processor chip designed in 65nm process, which requires the design target of 800MHz in the worst process conditions. The design of two-stage Cache is very important. In this paper, the physical design optimization technology of two-stage Cache in YHFT-DX chips and regular chips is studied. The main contents are as follows:. 1) the two-stage Cache adopts a split-body structure and divides the 1MB storage into 16 Bank bodies. Each Bank is composed of four SRAM_CELL basic modules. The circuit design of the SRAM_CELL module is studied, and its layout, routing method and decoding circuit are optimized. Finally, the layout of the module is reasonably planned. 2) the physical design of macro module Bank in the original sample chip is studied, and several methods such as in situ optimization are used for timing convergence, and the useful deviation technique is used to optimize the timing of long interconnect path. The layout structure of Bank volume in the whole chip is studied. The key paths and performance advantages and disadvantages of different layout structures are analyzed. Finally, the inverted U-shaped layout of Bank in the initial chip is determined. 3) the LRU(Least Recent use module is fully customized, the 13T memory cell with reset end is used, and compared with other memory cells in area, performance, noise tolerance and power consumption, the read-write operation circuit is designed. All the read operation circuits are implemented by combinatorial logic. The results of delay and power consumption are simulated. The fully customized design reduces critical path delay by 218ps. the timing performance is improved by 29 and the timing violation associated with LRU in the chip is eliminated. 4) physical design of normal chip two-level Cache is carried out by using hierarchical design method. The layout structure of Bank is adjusted, and the position of I / O port is optimized according to the interconnection relationship with other modules in the whole chip. The time sequence of cross-module path 80 is improved. The power supply network is designed, and the voltage drop is controlled within 3% while the power supply is sufficient. The clock tree synthesizes the binary tree topology of the balance tree. Several methods are used to optimize clock bias and noise. The effects of crosstalk on signal delay are analyzed, and the methods of crosstalk prevention and repair are studied, which can effectively improve the anti-noise ability of the design. 5) the hierarchical structure of the memory is reorganized in the normal chip, the two Bank bodies are merged into a single Bank2 module, the long interconnection of the remote memory cells is planned, and the routing rules of double linewidth and double spacing are adopted. By improving critical path delay 30, the timing violation caused by long interconnect in two stage Cache is effectively solved. Finally, compared with the original chip, the two-stage Cache delay of the standard chip is reduced by 90, the performance is improved by 6.7, and the design target of 800MHz is achieved under the worst process condition of 65nm.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333

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