本文選題：高速信號(hào)采集　切入點(diǎn)：數(shù)字信號(hào)處理　出處：《電子科技大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：高速發(fā)展的現(xiàn)代儀器儀表與自動(dòng)測(cè)試技術(shù)促使著人們開發(fā)出高性能、高穩(wěn)定性和易于系統(tǒng)集成的產(chǎn)品。數(shù)據(jù)采集與處理系統(tǒng)作為自動(dòng)測(cè)試技術(shù)的核心，他的采樣率、存儲(chǔ)深度、分辨率和靈活及穩(wěn)定性必然得到關(guān)注。而基于CompactPCIE、PXI/CompactPCI、VXI等總線的數(shù)據(jù)采集模塊因其便于系統(tǒng)集成和穩(wěn)定等特點(diǎn)，被廣泛應(yīng)用于自動(dòng)測(cè)試測(cè)量和工業(yè)自動(dòng)化領(lǐng)域。所以從提高采集系統(tǒng)帶寬、實(shí)時(shí)采樣率和存儲(chǔ)深度等方面研究CPCI數(shù)據(jù)采集處理模塊對(duì)整個(gè)測(cè)試系統(tǒng)有重大意義。 本文主要從基于CPCI總線的高速數(shù)據(jù)采集處理模塊的硬件實(shí)現(xiàn)和數(shù)字邏輯設(shè)計(jì)兩個(gè)方面進(jìn)行論述和分析，如數(shù)據(jù)采集存儲(chǔ)邏輯設(shè)計(jì)和電路設(shè)計(jì)、DDR2SO-DIMM控制器設(shè)計(jì)、CPCI接口電路設(shè)計(jì)以及數(shù)字信號(hào)處理邏輯設(shè)計(jì)等。 具體內(nèi)容包括： 1.從研究如何提升系統(tǒng)采樣率出發(fā)，得出基于時(shí)間交替并行采樣技術(shù)，以1片雙通道ADC來構(gòu)架400MSPS采樣設(shè)計(jì)方案。 2.分析采樣時(shí)鐘對(duì)采樣性能的影響，并依據(jù)系統(tǒng)采樣時(shí)鐘設(shè)計(jì)理論，設(shè)計(jì)實(shí)現(xiàn)了1.5GHz高頻時(shí)鐘產(chǎn)生與轉(zhuǎn)換的方案。 3.信號(hào)采集前端通道設(shè)計(jì)。實(shí)現(xiàn)高信噪比、高動(dòng)態(tài)范圍、信號(hào)增益與衰減可控的高速模擬信號(hào)通道； 4.根據(jù)系統(tǒng)存儲(chǔ)深度和速度要求，，完成基于DDR2SDRAM SO-DIMM的硬件實(shí)現(xiàn)和DDR2控制器的邏輯設(shè)計(jì)，該控制器能夠通過讀取DDR2SDRAM SO-DIMM上的SPD信息實(shí)現(xiàn)時(shí)間參數(shù)和地址位寬自適用。 5.利用PLX公司的專用的PCI接口芯片PCI9054實(shí)現(xiàn)CPCI接口電路設(shè)計(jì)和本地邏輯接口實(shí)現(xiàn)。 6.完成過采樣和數(shù)字濾波的邏輯設(shè)計(jì)，提高了采集精度和抗噪性能。 該設(shè)計(jì)實(shí)現(xiàn)了DDR2SO-DIMM的控制，能夠?qū)Σ杉臄?shù)據(jù)進(jìn)行存儲(chǔ)和數(shù)字化處理，滿足設(shè)計(jì)指標(biāo)要求，達(dá)到了預(yù)期目標(biāo)。
[Abstract]:The rapid development of modern instrumentation and automatic testing technology has prompted people to develop high performance, high stability and easy system integration products. Data acquisition and processing system as the core of automatic testing technology, its sampling rate, storage depth, Resolution, flexibility and stability must be paid close attention to. The data acquisition module based on PXI / CompactPCI VXI bus is easy to integrate and stable. It is widely used in the fields of automatic measurement and industrial automation, so it is of great significance to study the CPCI data acquisition and processing module from the aspects of improving the bandwidth of the acquisition system, real-time sampling rate and storage depth, etc. This paper mainly discusses and analyzes the hardware implementation and digital logic design of high-speed data acquisition and processing module based on CPCI bus. Such as data acquisition and storage logic design and circuit design DDR2SO-DIMM controller design CPCI interface circuit design and digital signal processing logic design and so on. Specific elements include:. 1. Based on the study of how to improve the sampling rate of the system, a 400MSPS sampling design scheme based on the time alternating parallel sampling technique and a dual-channel ADC is proposed. 2. The influence of sampling clock on sampling performance is analyzed. According to the system sampling clock design theory, a 1.5 GHz high frequency clock generation and conversion scheme is designed and realized. 3. Design of front-end channel for signal acquisition. High speed analog signal channel with high signal-to-noise ratio, high dynamic range, controllable signal gain and attenuation; 4. According to the requirement of system storage depth and speed, the hardware implementation based on DDR2SDRAM SO-DIMM and the logic design of DDR2 controller are completed. The controller can realize time parameter and address bit width self-adaptation by reading SPD information on DDR2SDRAM SO-DIMM. 5. The design of CPCI interface circuit and the realization of local logic interface are realized by PCI interface chip PCI9054 of PLX company. 6. The logic design of oversampling and digital filtering is completed, and the acquisition accuracy and anti-noise performance are improved. The design realizes the control of DDR2SO-DIMM, can store and digitize the collected data, meet the requirements of the design index and achieve the expected goal.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP274.2;TP336

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本文編號(hào)：1616880