本文選題：現(xiàn)場可編程門陣列　切入點：異構(gòu)計算　出處：《華東交通大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著單處理機計算速度和網(wǎng)絡(luò)技術(shù)的不斷提高與發(fā)展，計算機應(yīng)用范圍逐漸擴大，異構(gòu)計算系統(tǒng)在現(xiàn)實生活和工作中得到了廣泛運用。實時硬件任務(wù)調(diào)度與資源管理是異構(gòu)計算系統(tǒng)的關(guān)鍵問題，是研究中亟待解決的一個難題。 異構(gòu)計算的實時硬件任務(wù)調(diào)度目標(biāo)是在有限約束條件的前提下為實現(xiàn)一定性能指標(biāo)而盡量減少整個系統(tǒng)的處理時間。文中所提出的異構(gòu)計算系統(tǒng)是基于現(xiàn)場可編程門陣列FPGA加速的多結(jié)點處理系統(tǒng)。實時硬件任務(wù)調(diào)度分為全局系統(tǒng)調(diào)度和目標(biāo)處理結(jié)點的局部調(diào)度。在全局系統(tǒng)調(diào)度下，，本文針對最佳適應(yīng)算法Best-Fit的缺陷提出了性能更高的基于首適應(yīng)的最佳適應(yīng)算法BFBOFF；而在目標(biāo)處理器結(jié)點的局部調(diào)度下，本文在避免最大入侵的原則上提出了一種避免入侵最佳適應(yīng)算法AIBFA。通過實驗的性能仿真證實了BFBOFF算法和AIBFA算法分別降低了全局系統(tǒng)調(diào)度的平均時間負載率和目標(biāo)處理器結(jié)點局部調(diào)度的任務(wù)拒絕率。 本文對目標(biāo)處理結(jié)點上的FPGA資源管理的研究包括尋找空閑資源全集算法和任務(wù)在FPGA上的放置算法。高效的FPGA空閑資源管理策略對系統(tǒng)整體性起著非常重要的作用。針對尋找空閑資源全集的問題提出了一種基于單向棧的算法來尋找最大空閑矩形(MFR)，利用可重構(gòu)計算單元的不同M值進出單向棧來搜索到所有最大空閑矩形，通過實驗表明，算法通過使用單向棧與算法優(yōu)化，有效提高了查找空閑資源全集時的性能。硬件任務(wù)在FPGA上的放置就類似于軟件任務(wù)在計算機內(nèi)存中的運行，隨著硬件任務(wù)的放置，F(xiàn)PGA中的資源碎片可能會越來越多，這嚴重地影響著系統(tǒng)的整體性能，本文提出了一種基于二維空間鄰接度算法TDSADA法來減少FPGA資源的碎片率。
[Abstract]:With the improvement and development of the computing speed and network technology of single processor, the scope of computer application is gradually expanding. Heterogeneous computing systems have been widely used in real life and work. Real-time hardware task scheduling and resource management is a key problem in heterogeneous computing systems and a difficult problem to be solved. The real-time hardware task scheduling goal of heterogeneous computing is to minimize the processing time of the whole system in order to achieve certain performance index under the premise of limited constraints. The heterogeneous computing system proposed in this paper is based on the field capability. The real-time hardware task scheduling is divided into global system scheduling and local scheduling of target processing nodes. Aiming at the defects of the optimal adaptive algorithm (Best-Fit), this paper proposes a better adaptive algorithm based on the first adaptive algorithm (BFBOFF), which is based on the local scheduling of the target processor nodes. Based on the principle of avoiding maximum intrusion, this paper proposes an optimal intrusion avoidance algorithm, AIBFA.Through the performance simulation of experiments, it is proved that the BFBOFF algorithm and the AIBFA algorithm reduce the average time load rate and the target of global system scheduling, respectively. Task rejection rate for local scheduling of processor nodes. In this paper, the research of FPGA resource management on target processing node includes searching for the complete set of free resources and placing tasks on FPGA. Efficient FPGA free resource management strategy plays an important role in the system integrity. Aiming at the problem of finding the complete set of free resources, this paper presents an algorithm based on one-way stack to find the maximum free rectangle MFRN, and uses the different M values of the reconfigurable computing unit to find all the maximum free rectangles in and out of the one-way stack. The experiments show that the algorithm can effectively improve the performance of searching the complete set of free resources by using unidirectional stack and algorithm optimization. The placement of hardware tasks on FPGA is similar to the running of software tasks in computer memory. With the placement of hardware tasks, there may be more and more resource fragments in FPGA, which seriously affects the overall performance of the system. In this paper, a two-dimensional spatial adjacency algorithm (TDSADA) is proposed to reduce the fragmentation rate of FPGA resources.
【學(xué)位授予單位】：華東交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332;TP301.6

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本文編號：1615026