本文關(guān)鍵詞： 高速 流水線操作 LVDS ECC　出處：《中北大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：雷達(dá)技術(shù)隨著航空航天技術(shù)的極大提升，也逐漸趨向高分辨率等方向發(fā)展，同時這也給雷達(dá)加大了信息量，因此也給雷達(dá)數(shù)據(jù)記錄設(shè)備提出了更高要求。首先要求其大容量，目前用于雷達(dá)的數(shù)據(jù)記錄儀，容量要求一般均在幾十GB，有的已經(jīng)達(dá)到了幾百GB以上；其次要求高速度，以前的數(shù)據(jù)記錄儀一般只有幾KB/s，現(xiàn)在通常要求達(dá)到幾十MB/s，甚至上百MB/s；再是要求數(shù)據(jù)的可靠性，由于數(shù)據(jù)記錄儀一般工作的環(huán)境比較惡劣，再加上有時候電路設(shè)計的一些原因，導(dǎo)致數(shù)據(jù)位發(fā)生翻轉(zhuǎn)，，數(shù)據(jù)發(fā)生失真而影響數(shù)據(jù)的可靠性，而這也許就會帶來嚴(yán)重的后果，因此在設(shè)計數(shù)據(jù)記錄儀時也必須加入必要措施保證數(shù)據(jù)的可靠性。 本文圍繞如何采集存儲高速、大容量的雷達(dá)回波數(shù)據(jù)展開了研究。在國內(nèi)外發(fā)展現(xiàn)狀以及實際應(yīng)用需求的基礎(chǔ)上，提出了基于雷達(dá)回波信號高速存儲系統(tǒng)的總體設(shè)計方案。針對40MHz的回波信號，設(shè)計了132MHz的采樣率。為實現(xiàn)雙通道的低相位差，采用了時鐘芯片分配兩個通道的時鐘，并且在PCB走線時也會格外注意信號線長度的一致以保證信號的同步。對于采集中的高速大容量數(shù)據(jù)，使用了目前較為主流、成熟的LVDS技術(shù)進行數(shù)據(jù)傳輸。數(shù)據(jù)的存儲選擇了三星公司的NAND FLASH作為數(shù)據(jù)的存儲介質(zhì)，并使用了流水線技術(shù)、交錯雙平面操作等方法有效的解決了高速數(shù)據(jù)與NANDFLASH寫入速度過低的矛盾。采用了32片4GB的NAND FLASH搭建出128GB的存儲容量。 本文最后通過搭建系統(tǒng)測試平臺做出了大量的測試，從測試結(jié)果中能看出數(shù)據(jù)記錄儀存儲卡的存儲速度可達(dá)到88MB/s，并且數(shù)據(jù)經(jīng)校驗無錯誤，能有效的滿足任務(wù)需要，實現(xiàn)了對高速大容量數(shù)據(jù)的可靠存儲。
[Abstract]:With the development of aeronautics and astronautics technology, radar technology is gradually developing towards high resolution and other directions. At the same time, it also increases the amount of information for radar, and therefore puts forward higher requirements for radar data recording equipment. At present, the capacity requirements of the data recorders used in radar are generally in the tens of GBs, some of which have reached more than several hundred gigabytes; secondly, high speed is required. In the past, the data recorder generally had only a few KB / s, but now it is usually required to reach tens of MBs, or even hundreds of MB/ s. Again, the reliability of the data is required. Because the general working environment of the data recorder is relatively bad, and some reasons for sometimes designing circuits, The data bit is reversed and the data is distorted, which may bring serious consequences. Therefore, the necessary measures must be added to the design of the data recorder to ensure the reliability of the data. This paper focuses on how to collect and store radar echo data with high speed and large capacity. The overall design of high-speed storage system based on radar echo signal is presented. The sampling rate of 132MHz is designed for 40MHz echo signal. In order to realize the low phase difference between two channels, the clock chip is used to allocate the clock of two channels. And when the PCB is on the line, it will pay special attention to the consistency of the length of the signal line to ensure the synchronization of the signal. Mature LVDS technology is used for data transmission. Samsung's NAND FLASH is chosen as the storage medium for data storage, and pipeline technology is used to store the data. The interlaced double-plane operation effectively solves the contradiction between the high speed data and the low write speed of NANDFLASH. The storage capacity of 128GB is built by using 32 pieces of 4GB NANDFLASH. At the end of this paper, a large number of tests have been made by building the system test platform. From the test results, we can see that the storage speed of the memory card of the data recorder can reach 88MB / s, and the data can be checked without errors, which can effectively meet the needs of the task. The reliable storage of high speed and large capacity data is realized.
【學(xué)位授予單位】：中北大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333;TN957.51

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本文編號：1547213