本文關(guān)鍵詞： SOC IP核 APB總線 同步串行接口 Verilog HDL　出處：《西安電子科技大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：近年來(lái)SOC設(shè)計(jì)產(chǎn)業(yè)飛速發(fā)展，其設(shè)計(jì)復(fù)雜度也日趨增加。SOC設(shè)計(jì)領(lǐng)域面臨這兩大挑戰(zhàn)，一是以設(shè)計(jì)重用為目的的IP復(fù)用技術(shù)，二是以可復(fù)用IP核為基礎(chǔ)的IP互連技術(shù)。因此對(duì)IP復(fù)用技術(shù)的研究在SOC設(shè)計(jì)行業(yè)內(nèi)具有重要意義。同步串行接口技術(shù)是一種高速全雙工同步串行通信總線，具有線路簡(jiǎn)單，節(jié)約功耗等優(yōu)點(diǎn)，廣泛應(yīng)用于各類SOC設(shè)計(jì)中。論文設(shè)計(jì)的通用同步串行接口IP核，支持SPI、SSP和Microwire三種串行協(xié)議，可配置為主從模式與外部串行設(shè)備進(jìn)行數(shù)據(jù)通信。這種靈活的可配置性和通用性符合SOC設(shè)計(jì)技術(shù)發(fā)展方向，具有很高的實(shí)用價(jià)值。 隨著IP復(fù)用技術(shù)的推廣，片上總線技術(shù)也得到了迅速發(fā)展。本文分析對(duì)比了Wishbo ne、CoreConnect、Avalon、AMBA總線的技術(shù)特點(diǎn)。其中，AMBA總線配置簡(jiǎn)單、使用靈活、功能強(qiáng)大，并且擁有眾多第三方支持，，特別是AMBA總線架構(gòu)中的APB高級(jí)外設(shè)總線，具有技術(shù)簡(jiǎn)單、功耗低、實(shí)用性強(qiáng)的優(yōu)點(diǎn)，應(yīng)用前景廣闊。 根據(jù)自頂向下的設(shè)計(jì)思路，論述了基于APB總線的同步串行接口IP核的設(shè)計(jì)方法。首先分析設(shè)計(jì)目標(biāo)和需求，定義了模塊外部輸入輸出接口。然后根據(jù)設(shè)計(jì)功能劃分子模塊，給出完整IP核模塊結(jié)構(gòu)框圖，以及詳細(xì)端口和寄存器說(shuō)明。接著詳細(xì)討論了IP核各個(gè)子模塊的具體功能和設(shè)計(jì)思路。 根據(jù)驗(yàn)證計(jì)劃，使用Modelsim對(duì)SSI接口IP核的RTL代碼進(jìn)行了功能仿真。測(cè)試了模塊的寄存器讀寫(xiě)、中斷觸發(fā)和不同協(xié)議下的數(shù)據(jù)傳輸，仿真結(jié)果表明SSI接口IP核設(shè)計(jì)正確，功能符合設(shè)計(jì)要求。
[Abstract]:In recent years, with the rapid development of SOC design industry, its design complexity is increasing. SoC design field is faced with these two challenges. One is IP reuse technology, which aims at design reuse. The other is IP interconnection technology based on reusable IP core. Therefore, the research of IP multiplexing technology is of great significance in SOC design industry. Synchronous serial interface technology is a high-speed full-duplex synchronous serial communication bus with simple circuit. It is widely used in all kinds of SOC design. The universal synchronous serial interface IP core, which supports three serial protocols, SPI SSP and Microwire, is designed in this paper. It can be configured for master-slave mode to communicate with the external serial device. This flexible configuration and versatility are in line with the development direction of SOC design technology and have high practical value. With the popularization of IP reuse technology, the on-chip bus technology has been developed rapidly. This paper analyzes and compares the technical characteristics of Wishbo bus, which is simple, flexible, powerful, and has many third party support. Especially, the APB advanced peripheral bus in the AMBA bus architecture has the advantages of simple technology, low power consumption and strong practicability, and has a broad application prospect. According to the top-down design idea, the design method of synchronous serial interface IP core based on APB bus is discussed. Firstly, the design goal and requirement are analyzed, the external input and output interface of module is defined, and then the sub-module is divided according to the design function. The complete block diagram of IP core module, the detailed port and register description are given. Then, the specific functions and design ideas of each sub-module of IP core are discussed in detail. According to the verification plan, the RTL code of SSI interface IP core is simulated with Modelsim, and the register reading and writing, interrupt triggering and data transmission under different protocols are tested. The simulation results show that the design of SSI interface IP core is correct. The function meets the design requirements.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP336;TN47

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