本文關(guān)鍵詞： 驗(yàn)證 VMM SystemVerilog 參考模型　出處：《西安電子科技大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著數(shù)字集成電路規(guī)模越來(lái)越大,設(shè)計(jì)越來(lái)越復(fù)雜,驗(yàn)證的難度也隨之增加,設(shè)計(jì)新加一項(xiàng)功能,驗(yàn)證增加不止一條測(cè)試案例,實(shí)際項(xiàng)目中驗(yàn)證所占時(shí)間更是高達(dá)整個(gè)項(xiàng)目研發(fā)周期的70%,搭建高效的驗(yàn)證平臺(tái),開(kāi)發(fā)優(yōu)秀的驗(yàn)證環(huán)境,成了當(dāng)前集成電路設(shè)計(jì)工作的重要任務(wù)。 目前雙界面卡的應(yīng)用在國(guó)內(nèi)乃至國(guó)際迅猛發(fā)展,已經(jīng)證明了雙界面卡應(yīng)用的美好前景。本文就雙界面卡中符合ISO/IEC14443協(xié)議的非接觸射頻通訊接口模塊驗(yàn)證提出的一種更高效的驗(yàn)證方法,即在傳統(tǒng)的基于VMM采用隨機(jī)約束激勵(lì)的驗(yàn)證平臺(tái)中,加入高抽象語(yǔ)言SystemVerilog搭建的參考模型,參考模型提供的黃金響應(yīng)使得對(duì)DUT功能正確性的判定變得更加簡(jiǎn)單高效,參考模型的加入也使得注入錯(cuò)誤的驗(yàn)證得以輕松實(shí)現(xiàn),在驗(yàn)證平臺(tái)中加入?yún)⒖寄Ｐ痛蠓岣吡蓑?yàn)證效率,同時(shí)也提高了驗(yàn)證平臺(tái)的可重用性能、可移植性,縮短了芯片研發(fā)周期。 本論文首先介紹闡述了VMM驗(yàn)證方法學(xué),之后介紹ISO/IEC14443通訊協(xié)議以及DUT的RTL設(shè)計(jì)規(guī)范,隨后將傳統(tǒng)驗(yàn)證平臺(tái)與參考模型驗(yàn)證平臺(tái)做出比較說(shuō)明。本論文中,重點(diǎn)工作是設(shè)計(jì)編寫(xiě)射頻通訊接口的參考模型,論文中重點(diǎn)介紹說(shuō)明了參考模型設(shè)計(jì)方法以及代碼結(jié)構(gòu),參考模型設(shè)計(jì)編寫(xiě)完成后,嵌入到傳統(tǒng)的驗(yàn)證環(huán)境中,進(jìn)行前端RTL仿真,仿真結(jié)果表明,在傳統(tǒng)驗(yàn)證環(huán)境中加入?yún)⒖寄Ｐ湍芴岣唑?yàn)證的覆蓋率。
[Abstract]:As the scale of the digital integrated circuit becomes more and more complex , the design becomes more and more complex , the difficulty of verification is increased , the design of a new function is added , the verification is increased more than one test case , the verification in the actual project is more than 70 % of the whole project development cycle , a high - efficiency verification platform is built , and an excellent verification environment is developed , and the important task of the current integrated circuit design work is developed . At present , the application of the dual - interface card in the domestic and even the international swift development has proved the good prospect of the dual - interface card application . In this paper , a more efficient verification method is proposed for the verification of the non - contact radio frequency communication interface module conforming to the ISO / IEC 14443 protocol in the dual - interface card . In the verification platform based on the random constraint excitation in the dual - interface card , the reference model provided by the reference model makes the judgment of the correctness of the function of the DUT more simple and efficient , and the reference model adds a reference model to greatly improve the verification efficiency , and simultaneously improves the reusability and the portability of the verification platform , and shortens the development cycle of the chip . This paper first introduces the methodology of VMM verification , then introduces the ISO / IEC 14443 communication protocol and the RTL design specification of the DUT , and then compares the traditional verification platform with the reference model verification platform . In this paper , the emphasis work is to design the reference model of the radio frequency communication interface . In this paper , the design method of the reference model and the code structure are described in this paper . After the design of the reference model is completed , the design of the reference model is embedded in the traditional verification environment , and the RTL simulation is carried out . The simulation results show that the reference model can be added to the traditional verification environment to improve the coverage of verification .

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP334.7

【參考文獻(xiàn)】

相關(guān)期刊論文 前6條

1 劉錚,章兢;非接觸式IC卡中的射頻識(shí)別技術(shù)[J];信息技術(shù);2002年04期

2 邊紅麗;;非接觸IC卡技術(shù)及應(yīng)用漫談[J];金卡工程;2002年06期

3 遲志剛;高德遠(yuǎn);樊曉椏;靳戰(zhàn)鵬;;一種基于功能覆蓋率的驗(yàn)證環(huán)境的構(gòu)建方法[J];計(jì)算機(jī)工程與應(yīng)用;2006年05期

4 杜宇芳,張英莉;電視機(jī)安全檢驗(yàn)中的抗電強(qiáng)度試驗(yàn)[J];信息技術(shù);2002年04期

5 左航;金玉豐;;一種基于Vera的集成電路建模驗(yàn)證方法[J];計(jì)算機(jī)技術(shù)與發(fā)展;2007年01期

6 索中英;吳華;朱林戶;張官榮;;車(chē)牌自動(dòng)識(shí)別的圖像匹配追蹤算法[J];探測(cè)與控制學(xué)報(bào);2008年01期

，

本文編號(hào)：1537419