本文關(guān)鍵詞： 驗證 VMM SystemVerilog 參考模型　出處：《西安電子科技大學》2013年碩士論文　論文類型：學位論文

【摘要】：隨著數(shù)字集成電路規(guī)模越來越大,設計越來越復雜,驗證的難度也隨之增加,設計新加一項功能,驗證增加不止一條測試案例,實際項目中驗證所占時間更是高達整個項目研發(fā)周期的70%,搭建高效的驗證平臺,開發(fā)優(yōu)秀的驗證環(huán)境,成了當前集成電路設計工作的重要任務。 目前雙界面卡的應用在國內(nèi)乃至國際迅猛發(fā)展,已經(jīng)證明了雙界面卡應用的美好前景。本文就雙界面卡中符合ISO/IEC14443協(xié)議的非接觸射頻通訊接口模塊驗證提出的一種更高效的驗證方法,即在傳統(tǒng)的基于VMM采用隨機約束激勵的驗證平臺中,加入高抽象語言SystemVerilog搭建的參考模型,參考模型提供的黃金響應使得對DUT功能正確性的判定變得更加簡單高效,參考模型的加入也使得注入錯誤的驗證得以輕松實現(xiàn),在驗證平臺中加入?yún)⒖寄Ｐ痛蠓岣吡蓑炞C效率,同時也提高了驗證平臺的可重用性能、可移植性,縮短了芯片研發(fā)周期。 本論文首先介紹闡述了VMM驗證方法學,之后介紹ISO/IEC14443通訊協(xié)議以及DUT的RTL設計規(guī)范,隨后將傳統(tǒng)驗證平臺與參考模型驗證平臺做出比較說明。本論文中,重點工作是設計編寫射頻通訊接口的參考模型,論文中重點介紹說明了參考模型設計方法以及代碼結(jié)構(gòu),參考模型設計編寫完成后,嵌入到傳統(tǒng)的驗證環(huán)境中,進行前端RTL仿真,仿真結(jié)果表明,在傳統(tǒng)驗證環(huán)境中加入?yún)⒖寄Ｐ湍芴岣唑炞C的覆蓋率。
[Abstract]:As the scale of the digital integrated circuit becomes more and more complex , the design becomes more and more complex , the difficulty of verification is increased , the design of a new function is added , the verification is increased more than one test case , the verification in the actual project is more than 70 % of the whole project development cycle , a high - efficiency verification platform is built , and an excellent verification environment is developed , and the important task of the current integrated circuit design work is developed . At present , the application of the dual - interface card in the domestic and even the international swift development has proved the good prospect of the dual - interface card application . In this paper , a more efficient verification method is proposed for the verification of the non - contact radio frequency communication interface module conforming to the ISO / IEC 14443 protocol in the dual - interface card . In the verification platform based on the random constraint excitation in the dual - interface card , the reference model provided by the reference model makes the judgment of the correctness of the function of the DUT more simple and efficient , and the reference model adds a reference model to greatly improve the verification efficiency , and simultaneously improves the reusability and the portability of the verification platform , and shortens the development cycle of the chip . This paper first introduces the methodology of VMM verification , then introduces the ISO / IEC 14443 communication protocol and the RTL design specification of the DUT , and then compares the traditional verification platform with the reference model verification platform . In this paper , the emphasis work is to design the reference model of the radio frequency communication interface . In this paper , the design method of the reference model and the code structure are described in this paper . After the design of the reference model is completed , the design of the reference model is embedded in the traditional verification environment , and the RTL simulation is carried out . The simulation results show that the reference model can be added to the traditional verification environment to improve the coverage of verification .

【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP334.7

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本文編號：1537419