本文關(guān)鍵詞： PLB總線 DCR總線 SDRAM存儲器 SDRAM控制器　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著現(xiàn)代社會進(jìn)入了信息化時(shí)代,各種各樣的信息都得以快速發(fā)展,伴隨而來的是數(shù)據(jù)的存儲量越來越大,所以對存儲芯片的要求也越來越高。大容量、高安全性的高速存儲芯片已成為了時(shí)代發(fā)展的主流。SDRAM(Synchronous Dynamic Random Access Memory,同步動態(tài)隨機(jī)存儲器)憑借其集成度高、功耗低、可靠性高、處理能力強(qiáng)等優(yōu)勢成為最佳選擇。但是SDRAM卻具有復(fù)雜的時(shí)序,為了使其滿足日益增長的存儲需求,SDRAM存儲器的控制芯片應(yīng)運(yùn)而生。雖然SDRAM控制器已經(jīng)發(fā)展到了DDR4(Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory,雙倍速率的第四代同步動態(tài)隨機(jī)存儲器),但其設(shè)計(jì)復(fù)雜,成本較高。本文設(shè)計(jì)的SDRAM控制器正是為了解決這個(gè)問題。本文選擇可編程邏輯器件中廣泛使用的FPGA(Field-Programmable Gate Array,現(xiàn)場可編程門陣列),使用硬件描述語言Verilog,遵循自頂向下的設(shè)計(jì)思想實(shí)現(xiàn)對SDRAM控制器的設(shè)計(jì)。本文分析了SDRAM控制器的發(fā)展現(xiàn)狀,確認(rèn)其設(shè)計(jì)目標(biāo)。通過分析CoreConnect總線中的PLB(Processor Local Bus,處理器局部總線)總線協(xié)議、DCR(Device Control Register Bus,設(shè)備控制寄存器總線)總線協(xié)議,以及SDRAM存儲器的性能、特點(diǎn)、時(shí)序要求,設(shè)計(jì)出SDRAM控制器的各項(xiàng)性能指標(biāo)、所需實(shí)現(xiàn)功能以及其時(shí)序要求。隨后,對SDRAM控制器的各個(gè)模塊進(jìn)行詳細(xì)設(shè)計(jì)。因PLB總線時(shí)序和SDRAM存儲器的時(shí)序不同,故在接口轉(zhuǎn)換單元采用大量異步FIFO(First Input First Output,先入先出隊(duì)列)進(jìn)行跨時(shí)鐘域處理;在數(shù)據(jù)控制模塊后設(shè)計(jì)了校驗(yàn)和錯(cuò)誤檢測模塊,采取ECC校驗(yàn)和奇偶校驗(yàn)兩種檢驗(yàn)方式保證數(shù)據(jù)存儲的安全性;采用片選空間的起始、結(jié)束地址可編程,SDRAM的行列、邏輯Bank可編程的設(shè)計(jì)方法提高本設(shè)計(jì)的適用范圍。最后采用模塊級驗(yàn)證和系統(tǒng)級驗(yàn)證兩種方法對SDRAM控制器進(jìn)行驗(yàn)證,通過對波形圖的分析,本設(shè)計(jì)能夠?qū)崿F(xiàn)從PLB總線發(fā)送單拍、四字Line、八字Line、雙字Burst、四字Burst操作到SDRAM存儲器。通過大量的驗(yàn)證數(shù)據(jù)可得出結(jié)論:本文所設(shè)計(jì)的SDRAM控制器實(shí)現(xiàn)了從PLB總線向SDRAM存儲器發(fā)送數(shù)據(jù)的基本功能。本設(shè)計(jì)的成本低、設(shè)計(jì)簡單、占用資源少,其設(shè)計(jì)原理適用于同類SDRAM控制器,以及低成本的大容量存儲器。
[Abstract]:With the modern society has entered the information age, all kinds of information have been developed rapidly, accompanied by more and more data storage, so the demand for memory chips is also getting higher and higher. High-security high-speed memory chip has become the mainstream of the times. SDRAMN synchronous Dynamic Random Access memory (synchronous dynamic random access memory) has high integration, low power consumption and high reliability. Such advantages as strong processing power are the best choice. But SDRAM has complex timing, In order to satisfy the increasing storage demand, the control chip of SDRAM memory has come into being. Although the SDRAM controller has been developed to DDR4(Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access memory, and 4th generation synchronous dynamic random access memory with double rate, its design is complicated. The SDRAM controller designed in this paper is designed to solve this problem. This paper selects FPGA(Field-Programmable Gate Array, a field programmable gate array, which is widely used in programmable logic devices, and uses the hardware description language Verilog, following the top-down. In this paper, the development of SDRAM controller is analyzed, and the development of SDRAM controller is analyzed. By analyzing the PLB(Processor Local bus (PLB(Processor Local bus) bus protocol in the CoreConnect bus, the device control register bus bus protocol, and the performance, characteristics and timing requirements of the SDRAM memory, The performance indexes, functions and timing requirements of SDRAM controller are designed. Then, the modules of SDRAM controller are designed in detail. Because the timing of PLB bus is different from that of SDRAM memory, Therefore, a large number of asynchronous FIFO(First Input First output and first-in first-out queue are used in the interface conversion unit to process across the clock domain, and the checksum error detection module is designed after the data control module. Using ECC check and parity check to ensure the security of data storage, using the start of chip selection space, end address programmable SDRAM column, The logical Bank programmable design method improves the scope of application of the design. Finally, the SDRAM controller is verified by module level verification and system level verification. By analyzing the waveform diagram, the design can send a single beat from the PLB bus. Four word line, eight word line, two word burst, four word Burst operate to SDRAM memory. Through a lot of verification data, we can draw a conclusion: the SDRAM controller designed in this paper realizes the basic function of sending data from PLB bus to SDRAM memory. Its design principle is suitable for similar SDRAM controller and low cost mass memory.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TP333

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本文編號：1528224