本文關(guān)鍵詞： 測試臺 ATmega128 CH375 FPGA USB　出處：《中北大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著航空航天事業(yè)的飛速發(fā)展，力參地面測試臺由于其在對力學(xué)參數(shù)采編設(shè)備的綜合測試及分析中的重要作用，已經(jīng)成為了當(dāng)今航天系統(tǒng)中重要的科研項(xiàng)目之一。它可以模擬力參采編單元工作所需的各項(xiàng)參數(shù)，完成對采編單元功能和性能的測試，為采編單元的研究及改進(jìn)，或?qū)ζ溥M(jìn)行故障分析提供了重要的基礎(chǔ)和參考依據(jù)。 本文在分析任務(wù)中功能指標(biāo)要求的基礎(chǔ)上，重點(diǎn)研究了采用U盤數(shù)據(jù)存儲的方法及設(shè)計(jì)，并采用了模塊化的設(shè)計(jì)準(zhǔn)則，實(shí)現(xiàn)了具有U盤存儲功能的力參地面測試臺。本文主要完成的工作如下： (1)電源模塊：研究了電壓轉(zhuǎn)換的設(shè)計(jì)方法，使其可以為其他模塊提供多種電壓，并為采編單元供應(yīng)穩(wěn)定的27V電源及用于拉偏測試的27±3V電源； (2)信號源模塊：以FPGA為主要控制電路，將信號源下載至2塊靜態(tài)存儲器，并通過D/A轉(zhuǎn)換實(shí)現(xiàn)50路模擬信號源的發(fā)送，通過下載不同的數(shù)字量信號實(shí)現(xiàn)不同模擬信號源的發(fā)送； (3)在線讀數(shù)及U盤存儲模塊：在完成在線讀數(shù)功能的基礎(chǔ)上，研究了U盤存儲功能的設(shè)計(jì)方法，通過單片機(jī)控制CH375進(jìn)而實(shí)現(xiàn)U盤存儲功能。在線讀數(shù)功能的控制芯片F(xiàn)PGA設(shè)計(jì)采用兩級FIFO模塊用于數(shù)據(jù)緩存，將第一級FIFO的數(shù)據(jù)發(fā)送到U盤存儲模塊，上位機(jī)通過指令控制讀取第二級FIFO內(nèi)數(shù)據(jù)，緩解了計(jì)算機(jī)引起的丟數(shù)問題，保障了數(shù)據(jù)的準(zhǔn)確性。 測試臺通過與力參采編單元進(jìn)行聯(lián)試，能夠?qū)α⒉删巻卧母黜?xiàng)性能進(jìn)行檢測，同時U盤存儲功能為新一代測試臺的研制提供了技術(shù)支持。
[Abstract]:With the rapid development of aerospace industry, because of its important role in the comprehensive testing and analysis of mechanical parameters acquisition equipment, It has become one of the important scientific research projects in the space system nowadays. It can simulate the parameters needed for the work of the acquisition unit, complete the testing of the function and performance of the unit, and make the research and improvement of the unit. Or to carry on the fault analysis to provide the important foundation and the reference basis. On the basis of analyzing the requirement of function index in the task, this paper mainly studies the method and design of using U disk data storage, and adopts the modular design criterion. The main work of this paper is as follows:. (1) Power supply module: the design method of voltage conversion is studied, which can provide various voltages for other modules, and supply stable 27V power supply and 27 鹵3V power supply for measuring pull deviation for collecting and editing unit. (2) signal source module: with FPGA as the main control circuit, the signal source is downloaded to 2 static memory, and 50 analog signal sources are transmitted by D- A conversion, and different analog signal sources are sent by downloading different digital signals. 3) On-line reading and U disk storage module: on the basis of completing the on-line reading function, the design method of U disk storage function is studied. The control chip FPGA of on-line reading function is designed to use two-stage FIFO module for data cache, and the data of the first stage FIFO is sent to U disk storage module, and the data of the first stage FIFO is sent to the U disk storage module, and the data of the first stage FIFO is sent to the U disk storage module. The upper computer reads the data of the second level FIFO through command control, which alleviates the problem caused by the computer and ensures the accuracy of the data. The test table can test the performance of the force parameter collecting and editing unit by combining with the force parameter collecting and editing unit. At the same time, the U disk storage function provides the technical support for the development of the new generation test bench.
【學(xué)位授予單位】：中北大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333;V416.8

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本文編號：1525264