本文關(guān)鍵詞： 乘法器 標(biāo)準(zhǔn)單元庫(kù)擴(kuò)展 改進(jìn)的Booth編碼算法 Wallace樹(shù) 邏輯功效　出處：《浙江大學(xué)》2012年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：乘法器是微處理器中的重要部件,它的設(shè)計(jì)與實(shí)現(xiàn)直接影響著整個(gè)數(shù)字系統(tǒng)的性能,因此高性能乘法器的設(shè)計(jì)仍然被關(guān)注。另一方面,激烈的市場(chǎng)競(jìng)爭(zhēng)加速了產(chǎn)品的上市進(jìn)程,從而要求設(shè)計(jì)者盡量縮短設(shè)計(jì)時(shí)間。為了兼顧乘法器的性能和設(shè)計(jì)時(shí)間,通常使用基于標(biāo)準(zhǔn)單元庫(kù)的半定制設(shè)計(jì)方法。但是傳統(tǒng)的半定制設(shè)計(jì)方法受限于庫(kù)中標(biāo)準(zhǔn)單元有限的驅(qū)動(dòng)能力,無(wú)法實(shí)現(xiàn)最短路徑延時(shí)。為此,本文提出了基于標(biāo)準(zhǔn)單元庫(kù)擴(kuò)展的乘法器設(shè)計(jì)方法,消除了傳統(tǒng)方法的不足。 本文設(shè)計(jì)并實(shí)現(xiàn)17 bit×17 bit帶符號(hào)數(shù)字乘法器。為了提高乘法器的性能,采用改進(jìn)的Booth編碼算法,Wallace樹(shù)形結(jié)構(gòu),以及基于標(biāo)準(zhǔn)單元庫(kù)擴(kuò)展的設(shè)計(jì)方法。該方法使用邏輯功效模型分析乘法器的關(guān)鍵路徑,通過(guò)構(gòu)造驅(qū)動(dòng)能力更為完備的單元以實(shí)現(xiàn)關(guān)鍵路徑中每一級(jí)門(mén)功效相等,從而得到最短路徑延時(shí)。將TSMC 90nm標(biāo)準(zhǔn)單元庫(kù)擴(kuò)展得到擴(kuò)展單元庫(kù),使用兩個(gè)單元庫(kù)分別版圖實(shí)現(xiàn)數(shù)字乘法器,基于擴(kuò)展單元庫(kù)實(shí)現(xiàn)的乘法器速度提升10.87%。實(shí)驗(yàn)結(jié)果表明,基于標(biāo)準(zhǔn)單元庫(kù)擴(kuò)展的半定制設(shè)計(jì)方法可以有效提升電路的性能,這種方法尤其適用于電路負(fù)載過(guò)大的情況。
[Abstract]:Multiplier is an important component in microprocessor, its design and implementation directly affect the performance of the whole digital system, so the design of high performance multiplier is still concerned. On the other hand, fierce market competition accelerates the process of product marketing. The designer is required to shorten the design time as much as possible. The semi-custom design method based on standard cell library is usually used. However, the traditional semi-custom design method is limited by the limited drive ability of the standard unit in the library, so it can not achieve the shortest path delay. In this paper, a multiplier design method based on standard cell library extension is proposed, which eliminates the shortcomings of traditional methods. In this paper, a 17 bit 脳 17 bit signed digital multiplier is designed and implemented. In order to improve the performance of the multiplier, an improved Booth coding algorithm is proposed. The method uses logical efficacy model to analyze the critical path of multiplier, and constructs a more complete drive unit to achieve the equal efficiency of every step gate in the critical path. The TSMC 90nm standard cell library is extended to obtain the extended cell library, and the digital multiplier is implemented by using the two cell libraries respectively. The speed of the multiplier based on the extended cell library is increased by 10.87. the experimental results show that, The semi-custom design method based on the expansion of standard cell library can effectively improve the performance of the circuit. This method is especially suitable for the case of excessive circuit load.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類(lèi)號(hào)】：TP332.22

【引證文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前2條

1 李碧琛;基于可擴(kuò)展標(biāo)準(zhǔn)單元的電路設(shè)計(jì)方法研究[D];浙江大學(xué);2013年

2 李輝華;PowerPC處理器整數(shù)運(yùn)算單元的設(shè)計(jì)與實(shí)現(xiàn)[D];西安電子科技大學(xué);2013年

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本文編號(hào)：1508753