本文關(guān)鍵詞： NoC 自動(dòng)代碼生成技術(shù) 嵌入式系統(tǒng) 仿真器　出處：《天津工業(yè)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：由于半導(dǎo)體工藝和VLSI設(shè)計(jì)技術(shù)的快速發(fā)展,更多復(fù)雜和高性能需求的工作被應(yīng)用于嵌入式系統(tǒng)中。但是,隨著工藝尺寸越來(lái)越小,嵌入式在應(yīng)用方面對(duì)帶寬的需求不斷增多,使得傳統(tǒng)總線式的片上通信架構(gòu)面臨著越來(lái)越多的挑戰(zhàn)。由于NoC很好地?cái)U(kuò)展性、靈活性和傳輸并行性,使得它越來(lái)越受到人們的青睞。因此,NoC逐漸的替代了傳統(tǒng)的總線結(jié)構(gòu),成為了新興通信架構(gòu)。由于在設(shè)計(jì)片上網(wǎng)絡(luò)時(shí)需要考慮拓?fù)?緩沖器大小,路由算法和流量控制機(jī)制等許多參數(shù)。因此,對(duì)全系統(tǒng)的準(zhǔn)確評(píng)估對(duì)于NoC來(lái)說(shuō)是必不可少的,所以NoC仿真器的研究也變得越來(lái)越重要。而現(xiàn)有NoC仿真器在設(shè)計(jì)過(guò)程中,需要研究人員對(duì)NoC各模塊進(jìn)行描述,編寫成VHDL代碼。而不同體系結(jié)構(gòu)的NoC模塊的VHDL代碼大體上是相同的。顯然,編寫VHDL代碼的這個(gè)過(guò)程不僅浪費(fèi)大量時(shí)間還有可能因?yàn)槿藶椴僮髟诖a方面產(chǎn)生不必要的錯(cuò)誤。為了解決此問(wèn)題,本文提出了基于自動(dòng)代碼生成技術(shù)的NoC硬件仿真器-NOCsim。該仿真器采用把自動(dòng)代碼生成技術(shù)應(yīng)用在硬件NoC仿真器中的策略。該策略利用自動(dòng)代碼生成器自動(dòng)地生成與NoC各模塊相對(duì)應(yīng)的VHDL代碼,然后再在FPGA上對(duì)其進(jìn)行仿真。本文中,自動(dòng)代碼生成系統(tǒng)主要從XML建模文件、代碼模板和基于XML和代碼模板的自動(dòng)代碼生成器方面進(jìn)行設(shè)計(jì)。通過(guò)實(shí)驗(yàn)結(jié)果分析,發(fā)現(xiàn)本文提出的NoC仿真器在仿真相同的網(wǎng)絡(luò)時(shí),在速度、面積利用率等性能方面與Booksim相比有了很大的提升,并且通過(guò)實(shí)驗(yàn)可以發(fā)現(xiàn)NOCsim能夠很好地仿真三維NoC。
[Abstract]:With the rapid development of semiconductor process and VLSI design technology, more and more complex and high performance requirements have been applied to embedded systems. The traditional on-chip communication architecture is facing more and more challenges. Because of its scalability, flexibility and parallelism, NoC is becoming more and more popular. Therefore, it has gradually replaced the traditional bus architecture. It has become a new communication architecture. It is necessary for NoC to evaluate the whole system accurately because many parameters, such as topology, buffer size, routing algorithm and flow control mechanism, need to be taken into account when designing the on-chip network. Therefore, the research of NoC simulator is becoming more and more important. In the design process of the existing NoC emulator, researchers need to describe each module of NoC. Write as VHDL code. The VHDL code for different architecture NoC modules is largely the same. Obviously, This process of writing VHDL code is not only a waste of time, but also the possibility of unnecessary errors in code caused by human manipulation. This paper presents a NoC hardware emulator based on automatic code generation technology-NOCsim. this simulator adopts the strategy of applying automatic code generation technology to hardware NoC simulator. The strategy uses automatic code generator to automatically generate and. The VHDL code corresponding to each module of NoC, In this paper, the automatic code generation system is designed mainly from XML modeling file, code template and automatic code generator based on XML and code template. It is found that the proposed NoC simulator can greatly improve the performance of Booksim in terms of speed, area utilization ratio and so on when simulating the same network, and it can be found that NOCsim can simulate 3D Noc well through experiments.
【學(xué)位授予單位】：天津工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN47;TP337

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本文編號(hào)：1507863