本文關(guān)鍵詞： 微控制器 精簡(jiǎn)指令集計(jì)算機(jī) ARM指令集 片上系統(tǒng) 片上總線(xiàn)　出處：《浙江理工大學(xué)》2013年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：嵌入式系統(tǒng)在很多領(lǐng)域有著廣泛的應(yīng)用，包括個(gè)人消費(fèi)、通信、工業(yè)控制以及軍事等。嵌入式系統(tǒng)的核心是微控制器，，其性能直接影響到整個(gè)系統(tǒng)的性能。本文基于開(kāi)源IP核設(shè)計(jì)并實(shí)現(xiàn)了一款具備基本功能的微控制器，該微控制器用于一款小型射頻SOC芯片。該微控制器的核心是一個(gè)基于ARMv4指令集微處理器內(nèi)核，外圍設(shè)備包括SPI控制器、通用串口、定時(shí)器、通用IO接口和外部中斷以及中斷控制器。 本文設(shè)計(jì)的微處理器是在一款基于ARMv2a指令集架構(gòu)的開(kāi)源IP核的基礎(chǔ)上，進(jìn)行深度修改得到。ARM作為目前RISC（Reduced Instruction Set Computer），即精簡(jiǎn)指令集計(jì)算機(jī)的代表，在嵌入式領(lǐng)域有著廣泛的應(yīng)用，本文選擇ARM指令集有著深遠(yuǎn)意義。本文設(shè)計(jì)的微處理器內(nèi)核兼容ARMv4指令集48條指令中的43條，5條協(xié)處理器指令除外。該微處理器內(nèi)核擁有三級(jí)流水線(xiàn)結(jié)構(gòu)和Wishbone系統(tǒng)總線(xiàn)，而且能夠很好的兼容現(xiàn)有編譯器，方便應(yīng)用調(diào)試。 外圍設(shè)備也是微控制器的重要組成部分，微處理器影響著微控制器的性能，而外圍設(shè)備則關(guān)系到整個(gè)微控制器功能的豐富性。本文設(shè)計(jì)的微控制器包括了五個(gè)外圍設(shè)備，其中SPI控制器和通用串口是參考現(xiàn)有案例自主重點(diǎn)設(shè)計(jì)，定時(shí)器、通用IO接口及外部中斷和中斷控制器只具備簡(jiǎn)單功能，為滿(mǎn)足射頻SOC基本需求而設(shè)置。SPI控制器符合SPI通信協(xié)議標(biāo)準(zhǔn)；通用串口具有最基本的數(shù)據(jù)幀結(jié)構(gòu)，即1位起始位、8位寬的數(shù)據(jù)位、沒(méi)有校驗(yàn)位，停止位位2位。所有外設(shè)都基于Wishbone系統(tǒng)總線(xiàn)從設(shè)備而設(shè)計(jì)，不僅應(yīng)用于本文的微控制器，還可以應(yīng)用于其他任何基于Wishbone系統(tǒng)總線(xiàn)的設(shè)計(jì)。 仿真驗(yàn)證是數(shù)字系統(tǒng)設(shè)計(jì)的重要流程，包括功能仿真和布局布線(xiàn)后的仿真。本文設(shè)計(jì)的微控制器從整體到各個(gè)功能模塊都進(jìn)行了完整的仿真，功能仿真所使用的仿真工具是Modelsim6.5f版本；由于沒(méi)有目標(biāo)工藝庫(kù)，因此布局布線(xiàn)后的仿真是針對(duì)Altera公司的CycloneII系列FPGA進(jìn)行的。通過(guò)最后微控制器在FPGA上的測(cè)試，證明整個(gè)設(shè)計(jì)實(shí)現(xiàn)了完整的微控制器功能，能夠滿(mǎn)足射頻SOC對(duì)微控制器的需求。
[Abstract]:Embedded systems are widely used in many fields, including personal consumption, communication, industrial control, military and so on. The core of embedded system is microcontroller. Its performance directly affects the performance of the whole system. This paper designs and implements a microcontroller with basic functions based on open source IP core. The microcontroller is used in a small RF SOC chip. The core of the microcontroller is a microprocessor kernel based on ARMv4 instruction set. The peripheral devices include SPI controller, universal serial port, timer, etc. General IO interface and external interrupt and interrupt controller. The microprocessor designed in this paper is based on an open source IP core based on ARMv2a instruction set architecture, and gets the. Arm as the representative of RISC(Reduced Instruction Set computer, which is widely used in embedded field. The selection of ARM instruction set in this paper is of far-reaching significance. The microprocessor kernel designed in this paper is compatible with 43 or 5 coprocessor instructions of the 48 instructions of the ARMv4 instruction set. The microprocessor core has a three-level pipeline structure and a Wishbone system bus. And can be very good compatible with the existing compiler, easy to apply debugging. The peripheral equipment is also an important part of the microcontroller. The microprocessor affects the performance of the microcontroller, and the peripheral device is related to the richness of the function of the whole microcontroller. The microcontroller designed in this paper includes five peripherals. The SPI controller and the general serial port are designed independently with reference to the existing cases. The timer, the general IO interface and the external interrupt and interrupt controller have only simple functions. In order to meet the basic requirements of RF SOC, the. SPI controller conforms to the standard of SPI communication protocol, the universal serial port has the most basic data frame structure, that is, 1 bit starting bit and 8 bit wide data bit, there is no check bit, All peripherals are designed based on Wishbone system bus slave device, which can be applied not only to the microcontroller in this paper, but also to any other design based on Wishbone system bus. Simulation verification is an important flow of digital system design, including function simulation and layout and routing simulation. The simulation tool used in functional simulation is the Modelsim6.5f version. Because there is no target process library, the simulation after layout and routing is done for Altera's CycloneII series FPGA. Finally, the microcontroller is tested on FPGA. It is proved that the whole design realizes the complete function of microcontroller and can meet the demand of RF SOC for microcontroller.
【學(xué)位授予單位】：浙江理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類(lèi)號(hào)】：TP332;TN47

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