本文關(guān)鍵詞： 數(shù)字視頻接口 最小轉(zhuǎn)換差分信號(hào) 電荷泵鎖相環(huán) 并串轉(zhuǎn)換 T.M.D.S.驅(qū)動(dòng) 版圖　出處：《國防科學(xué)技術(shù)大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：DVI（Digital Visual Interface，數(shù)字視頻接口）作為一種優(yōu)秀接口標(biāo)準(zhǔn)的提出，滿足了人們對(duì)顯示設(shè)備高分辨率和高刷新率的要求。相對(duì)于傳統(tǒng)的模擬顯示設(shè)備，其穩(wěn)定性和顯示性能得到了加強(qiáng)，而且更進(jìn)一步地降低了平板顯示器的成本。DVI接口已經(jīng)成為當(dāng)今數(shù)字顯示技術(shù)中廣泛采用的接口之一。 本文以DVI接口通訊協(xié)議為基礎(chǔ)，詳細(xì)介紹并分析其基本電氣鏈接—TMDS（Transition Minimized Differential Signaling，最小轉(zhuǎn)換差分信號(hào)）技術(shù)，，成功設(shè)計(jì)并實(shí)現(xiàn)了一款用于DVI接口發(fā)送器的物理層電路。為滿足DVI1.0標(biāo)準(zhǔn)的要求，該電路輸入時(shí)鐘信號(hào)頻率在：25MHz~165MHz，鏈路高速串行數(shù)據(jù)傳輸速率在：250Mbps~1.65Gbps。為解決輸入信號(hào)頻率范圍寬、數(shù)據(jù)傳輸速率高等問題，本文主要做出了如下幾個(gè)方面的研究與創(chuàng)新： 1、深入研究DVI1.0協(xié)議規(guī)范，對(duì)DVI發(fā)送器進(jìn)行系統(tǒng)結(jié)構(gòu)定義和功能模塊劃分。 2、設(shè)計(jì)一種用于產(chǎn)生時(shí)鐘信號(hào)十倍頻的電荷泵鎖相環(huán)。在進(jìn)行鎖相環(huán)數(shù)學(xué)模型分析的基礎(chǔ)上，應(yīng)用Simulink工具建模仿真，為后續(xù)各個(gè)模塊的參數(shù)設(shè)定提供理論指導(dǎo)。改進(jìn)了本文的電荷泵電路，采用“自舉電路”消除鎖相環(huán)非理想效應(yīng)中電荷共享等問題；改進(jìn)了三級(jí)環(huán)形壓控振蕩器電路，采用交叉耦合式延遲單元產(chǎn)生快速理想的全擺幅差分輸出。仿真結(jié)果表明，輸入信號(hào)在頻率范圍25MHz~165MHz條件下，鎖相環(huán)電路均能正常工作，且鎖定時(shí)間均小于2μs，噪聲抖動(dòng)測試峰-峰值抖動(dòng)均小于2.5%。 3、設(shè)計(jì)一款用于高速串行數(shù)據(jù)傳輸?shù)尿?qū)動(dòng)器電路。對(duì)比各接口標(biāo)準(zhǔn)電路結(jié)構(gòu)，提出簡化的電流模主體驅(qū)動(dòng)電路，實(shí)現(xiàn)了滿足DVI1.0協(xié)議要求的低擺幅（400mV~600mV）差分信號(hào)傳輸，鏈路帶寬達(dá)到1.65GHz，滿足設(shè)計(jì)要求。改進(jìn)了電平轉(zhuǎn)換電路，實(shí)現(xiàn)從內(nèi)核電路1.2V電壓域到外部傳輸電路3.3V電壓域的轉(zhuǎn)換，降低了電磁干擾對(duì)傳輸信號(hào)的影響，很好地滿足高頻信號(hào)傳輸?shù)男枰?4、采用SMIC0.11μm、1P8M（單層多晶硅八層金屬）、1.2V/3.3V混合信號(hào)CMOS工藝，完成整體電路的版圖設(shè)計(jì)，芯片面積為121.66μm116.16μm。
[Abstract]:As an excellent interface standard, DVI(Digital Visual Interface (Digital Video Interface) meets the requirements of high resolution and high refresh rate of display devices. Compared with traditional analog display devices, its stability and performance are enhanced. Furthermore, it reduces the cost of flat panel display. DVI interface has become one of the widely used interfaces in digital display technology. Based on the DVI interface communication protocol, this paper introduces and analyzes the basic electrical link (TMDS transition Minimized Differential signaling) technology in detail. A physical layer circuit for DVI interface transmitter is successfully designed and implemented. In order to meet the requirements of DVI1.0 standard, the clock signal frequency of the circuit is at: 25MHz / 165MHz, and the link high-speed serial data transmission rate is at: 250Mbps1.65Gbps.In order to solve the problem, the input signal frequency range is wide. High data transmission rate, this paper mainly made the following aspects of research and innovation:. 1. Deeply study the DVI1.0 protocol specification, define the system structure and partition the function module of the DVI transmitter. 2. A charge pump phase-locked loop (CPPLL), which is used to generate clock signal 10 times frequency, is designed. Based on the mathematical model analysis of PLL, the Simulink tool is used to model and simulate the PLL. This paper improves the charge pump circuit in this paper, adopts "bootstrap circuit" to eliminate the problem of charge sharing in the non-ideal effect of phase-locked loop, and improves the three-stage ring voltage-controlled oscillator circuit. A fast and ideal full swing differential output is generated by cross-coupled delay unit. The simulation results show that the input signal can work normally in the frequency range of 25MHz / 165MHz. The locking time is less than 2 渭 s, and the peak to peak jitter of noise jitter is less than 2.5 渭 s. 3. A driver circuit for high speed serial data transmission is designed. Compared with the standard circuit structure of each interface, a simplified current-mode main driver circuit is proposed to realize the differential signal transmission with low swing of 400mV / 600mV, which meets the requirements of DVI1.0 protocol. The link bandwidth reaches 1.65 GHz, which meets the design requirements. The level conversion circuit is improved to realize the conversion from 1.2 V voltage domain of the core circuit to 3.3 V voltage domain of the external transmission circuit, which reduces the influence of electromagnetic interference on the transmission signal. It can meet the needs of high frequency signal transmission. 4. The SMIC0.11 渭 m 1P8M (single layer polysilicon 8-layer metal / metal / 1.2V / 3.3V mixed signal CMOS process) is used to complete the layout design of the whole circuit. The chip area is 121.66 渭 m 116.16 渭 m.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP334.7

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相關(guān)期刊論文 前1條

1 姜梅,劉三清,李乃平,陳釗;用于電荷泵鎖相環(huán)的無源濾波器的設(shè)計(jì)[J];微電子學(xué);2003年04期

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